From 7b3fe404ab30767a8b65f61fa2a6eebbe9019641 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Fri, 31 Jan 2020 18:20:22 -0300 Subject: $readmem[hb] file inclusion is now relative to the Verilog file Signed-off-by: Rodrigo Alejandro Melo --- frontends/ast/simplify.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b94a8d710..f7364b9a8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2886,7 +2886,8 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m int meminit_size=0; std::ifstream f; - f.open(mem_filename.c_str()); + std::string path = filename.substr(0, filename.find_last_of("\\/")+1); + f.open(path + mem_filename.c_str()); yosys_input_files.insert(mem_filename); if (f.fail()) -- cgit v1.2.3