From 1c6f0cffd95876eac620bdfe9be50b366dabd8c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 12:27:07 -0700 Subject: Cope with an output having same name as an input (i.e. CO) --- frontends/aiger/aigerparse.cc | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b752d3127..0b0f6dd2e 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -460,12 +460,30 @@ next_line: log_assert(wire); log_assert(wire->port_output); - if (index == 0) - module->rename(wire, escaped_symbol); + if (index == 0) { + // Cope with the fact that a CO might be identical + // to a PO (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_symbol); + if (!existing) + module->rename(wire, escaped_symbol); + else { + wire->port_output = false; + module->connect(wire, existing); + } + } else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + } + else { + module->connect(wire, existing); + wire->port_output = false; + } } } else -- cgit v1.2.3 From ada130b4599db74744df34d8608611fd746bf08a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 16:17:12 -0700 Subject: Also cope with duplicated CIs --- frontends/aiger/aigerparse.cc | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0b0f6dd2e..0d81cc2fd 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -446,12 +446,30 @@ next_line: log_assert(wire); log_assert(wire->port_input); - if (index == 0) - module->rename(wire, escaped_symbol); + if (index == 0) { + // Cope with the fact that a CI might be identical + // to a PI (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_symbol); + if (!existing) + module->rename(wire, escaped_symbol); + else { + wire->port_input = false; + module->connect(wire, existing); + } + } else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + } + else { + module->connect(wire, existing); + wire->port_input = false; + } } } else if (type == "output") { -- cgit v1.2.3 From acf3f5694bb0cd9911566855df27c17e7e82b8cc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 17:02:24 -0700 Subject: Fix inout handling for -map option --- frontends/aiger/aigerparse.cc | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b752d3127..009b28455 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -439,7 +439,7 @@ next_line: std::string type, symbol; int variable, index; while (mf >> type >> variable >> index >> symbol) { - RTLIL::IdString escaped_symbol = RTLIL::escape_id(symbol); + RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); if (type == "input") { log_assert(static_cast(variable) < inputs.size()); RTLIL::Wire* wire = inputs[variable]; @@ -447,11 +447,11 @@ next_line: log_assert(wire->port_input); if (index == 0) - module->rename(wire, escaped_symbol); + module->rename(wire, escaped_s); else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); + module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index)); if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); } } else if (type == "output") { @@ -460,12 +460,32 @@ next_line: log_assert(wire); log_assert(wire->port_output); - if (index == 0) - module->rename(wire, escaped_symbol); - else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + if (index == 0) { + if (escaped_s.ends_with("$inout.out")) { + wire->port_output = false; + RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10)); + log_assert(in_wire); + log_assert(in_wire->port_input && !in_wire->port_output); + in_wire->port_output = true; + module->connect(in_wire, wire); + } + else + module->rename(wire, escaped_s); + } + else if (index > 0) { + if (escaped_s.ends_with("$inout.out")) { + wire->port_output = false; + RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index)); + log_assert(in_wire); + log_assert(in_wire->port_input && !in_wire->port_output); + in_wire->port_output = true; + module->connect(in_wire, wire); + } + else { + module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index)); + if (wideports) + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); + } } } else -- cgit v1.2.3 From 9bfcd8006378dc0d81a1c902501a6efeb8406cba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 18:21:16 -0700 Subject: Handle __dummy_o__ and __const[01]__ in read_aiger not abc --- frontends/aiger/aigerparse.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7e91c8cac..e35a8ad62 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -477,6 +477,10 @@ next_line: RTLIL::Wire* wire = outputs[variable]; log_assert(wire); log_assert(wire->port_output); + if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) { + wire->port_output = false; + continue; + } if (index == 0) { // Cope with the fact that a CO might be identical -- cgit v1.2.3 From fecafb2207efc772fec49b357bc6e20ca6a25aca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 18:22:44 -0700 Subject: Forgot backslashes --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e35a8ad62..f2d21f1db 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -477,7 +477,7 @@ next_line: RTLIL::Wire* wire = outputs[variable]; log_assert(wire); log_assert(wire->port_output); - if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) { + if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { wire->port_output = false; continue; } -- cgit v1.2.3