From eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 4 May 2020 10:22:05 -0700 Subject: verilog: set src attribute for primitives --- frontends/verilog/verilog_parser.y | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4a5aba79e..f2ff685e9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1747,7 +1747,9 @@ single_prim: /* no name */ { astbuf2 = astbuf1->clone(); ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')'; + } '(' cell_port_list ')' { + SET_AST_NODE_LOC(astbuf2, @1, @$); + } cell_parameter_list_opt: '#' '(' cell_parameter_list ')' | /* empty */; -- cgit v1.2.3