From 6378e2cd46711fed551ecf3201cee1f174d7053d Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Sun, 4 Mar 2018 23:35:08 +0200
Subject: First draft of Verilog parser support for specify blocks and
 parameters. The only functionality of this code at the moment is to accept
 correct specify syntax and ignore it. No part of the specify block is added
 to the AST

---
 frontends/verilog/verilog_lexer.l  |   3 +
 frontends/verilog/verilog_parser.y | 169 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 170 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d6d00c371..32d7738cf 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -145,6 +145,9 @@ YOSYS_NAMESPACE_END
 "endfunction"  { return TOK_ENDFUNCTION; }
 "task"         { return TOK_TASK; }
 "endtask"      { return TOK_ENDTASK; }
+"specify"      { return TOK_SPECIFY; }
+"endspecify"   { return TOK_ENDSPECIFY; }
+"specparam"    { return TOK_SPECPARAM; }
 "package"      { SV_KEYWORD(TOK_PACKAGE); }
 "endpackage"   { SV_KEYWORD(TOK_ENDPACKAGE); }
 "parameter"    { return TOK_PARAMETER; }
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ba2fc036e..3dd54f532 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -110,7 +110,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
-%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
+%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
@@ -476,7 +476,7 @@ module_body:
 	/* empty */;
 
 module_body_stmt:
-	task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt |
+	task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
 	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl;
 
 checker_decl:
@@ -634,6 +634,171 @@ task_func_body:
 	task_func_body behavioral_stmt |
 	/* empty */;
 
+specify_block:
+	TOK_SPECIFY specify_item_opt TOK_ENDSPECIFY |
+	TOK_SPECIFY TOK_ENDSPECIFY ;
+
+specify_item_opt:
+	specify_item_opt specify_item |
+	specify_item ;
+
+specify_item:
+	specparam_declaration
+	// | pulsestyle_declaration
+	// | showcancelled_declaration
+	| path_declaration
+	// | system_timing_declaration
+	;
+
+specparam_declaration:
+	TOK_SPECPARAM list_of_specparam_assignments ';' |
+	TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ;
+
+// IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match
+// and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005
+// exxxxtending this for SV specparam would change this anyhow
+specparam_range:
+	'[' constant_expression ':' constant_expression ']' ;
+
+list_of_specparam_assignments:
+	specparam_assignment | list_of_specparam_assignments ',' specparam_assignment;
+
+specparam_assignment:
+	TOK_ID '=' constant_mintypmax_expression ;
+
+/*
+pulsestyle_declaration :
+	;
+
+showcancelled_declaration :
+	;
+*/
+
+path_declaration :
+	simple_path_declaration
+	// | edge_sensitive_path_declaration
+	// | state_dependent_path_declaration
+	;
+
+simple_path_declaration :
+	parallel_path_description '=' path_delay_value ';'
+	// | full_path_description '=' path_delay_value ';'
+	;
+
+path_delay_value :
+	//list_of_path_delay_expressions
+	'(' list_of_path_delay_expressions ')'
+	;
+
+list_of_path_delay_expressions :
+/*
+	t_path_delay_expression
+	| trise_path_delay_expression ',' tfall_path_delay_expression
+	| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression
+	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
+	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
+	| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
+	  tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
+	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
+	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
+*/
+	path_delay_expression
+	| path_delay_expression ',' path_delay_expression
+	| path_delay_expression ',' path_delay_expression ',' path_delay_expression
+	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
+	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
+	;
+
+parallel_path_description :
+	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
+
+opt_polarity_operator :
+	'+'
+	| '-'
+	| ;
+
+// Good enough for the time being
+specify_input_terminal_descriptor :
+	TOK_ID ;
+
+// Good enough for the time being
+specify_output_terminal_descriptor :
+	TOK_ID ;
+
+/*
+system_timing_declaration :
+	;
+*/
+
+/*
+t_path_delay_expression :
+	path_delay_expression;
+
+trise_path_delay_expression :
+	path_delay_expression;
+
+tfall_path_delay_expression :
+	path_delay_expression;
+
+tz_path_delay_expression :
+	path_delay_expression;
+
+t01_path_delay_expression :
+	path_delay_expression;
+
+t10_path_delay_expression :
+	path_delay_expression;
+
+t0z_path_delay_expression :
+	path_delay_expression;
+
+tz1_path_delay_expression :
+	path_delay_expression;
+
+t1z_path_delay_expression :
+	path_delay_expression;
+
+tz0_path_delay_expression :
+	path_delay_expression;
+
+t0x_path_delay_expression :
+	path_delay_expression;
+
+tx1_path_delay_expression :
+	path_delay_expression;
+
+t1x_path_delay_expression :
+	path_delay_expression;
+
+tx0_path_delay_expression :
+	path_delay_expression;
+
+txz_path_delay_expression :
+	path_delay_expression;
+
+tzx_path_delay_expression :
+	path_delay_expression;
+*/
+
+path_delay_expression :
+	constant_mintypmax_expression;
+
+constant_mintypmax_expression :
+	constant_expression
+	| constant_expression ':' constant_expression ':' constant_expression
+	;
+
+// for the time being this is OK, but we may write our own expr here.
+// as I'm not sure it is legal to use a full expr here (probably not)
+// On the other hand, other rules requiring constant expressions also use 'expr'
+// (such as param assignment), so we may leave this as-is, perhaps assing runtime checks for constant-ness
+constant_expression:
+	expr ;
+
 param_signed:
 	TOK_SIGNED {
 		astbuf1->is_signed = true;
-- 
cgit v1.2.3


From 5ea2c53604aefeeaf43a638fe3c86813e947dc37 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 6 Apr 2018 14:35:11 +0200
Subject: Add read_verilog anyseq/anyconst/allseq/allconst attribute support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3dd54f532..47a5ddfa5 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -933,11 +933,43 @@ wire_name_list:
 
 wire_name_and_opt_assign:
 	wire_name {
-		if (current_wire_rand) {
+		bool attr_anyconst = false;
+		bool attr_anyseq = false;
+		bool attr_allconst = false;
+		bool attr_allseq = false;
+		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
+			delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
+			ast_stack.back()->children.back()->attributes.erase("\\anyconst");
+			attr_anyconst = true;
+		}
+		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
+			delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
+			ast_stack.back()->children.back()->attributes.erase("\\anyseq");
+			attr_anyseq = true;
+		}
+		if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
+			delete ast_stack.back()->children.back()->attributes.at("\\allconst");
+			ast_stack.back()->children.back()->attributes.erase("\\allconst");
+			attr_allconst = true;
+		}
+		if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
+			delete ast_stack.back()->children.back()->attributes.at("\\allseq");
+			ast_stack.back()->children.back()->attributes.erase("\\allseq");
+			attr_allseq = true;
+		}
+		if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
 			AstNode *wire = new AstNode(AST_IDENTIFIER);
 			AstNode *fcall = new AstNode(AST_FCALL);
 			wire->str = ast_stack.back()->children.back()->str;
 			fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
+			if (attr_anyconst)
+				fcall->str = "\\$anyconst";
+			if (attr_anyseq)
+				fcall->str = "\\$anyseq";
+			if (attr_allconst)
+				fcall->str = "\\$allconst";
+			if (attr_allseq)
+				fcall->str = "\\$allseq";
 			fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
 		}
-- 
cgit v1.2.3


From 66ffc99695107808bd5fe0c8d09cf386dcb269fd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 12 Apr 2018 14:28:28 +0200
Subject: Allow "property" in immediate assertions

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 47a5ddfa5..ef4e03a1a 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1236,39 +1236,42 @@ opt_label:
 		$$ = NULL;
 	};
 
+opt_property:
+	TOK_PROPERTY | /* empty */;
+
 assert:
-	TOK_ASSERT '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $3));
+	TOK_ASSERT opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4));
 	} |
-	TOK_ASSUME '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
+	TOK_ASSUME opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
 	} |
-	TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4));
+	TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
 	} |
-	TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
+	TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
 	} |
-	TOK_COVER '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3));
+	TOK_COVER opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
 	} |
-	TOK_COVER '(' ')' ';' {
+	TOK_COVER opt_property '(' ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
 	} |
 	TOK_COVER ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
 	} |
-	TOK_RESTRICT '(' expr ')' ';' {
+	TOK_RESTRICT opt_property '(' expr ')' ';' {
 		if (norestrict_mode)
-			delete $3;
+			delete $4;
 		else
-			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
+			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
 	} |
-	TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' {
+	TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode)
-			delete $4;
+			delete $5;
 		else
-			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
+			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
 	};
 
 assert_property:
-- 
cgit v1.2.3


From 2d7f3123f0c74cafcacc18f25e14cd8bba703b4e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 13 Apr 2018 11:52:28 +0200
Subject: Add statement labels for immediate assertions

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 39 ++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ef4e03a1a..e803d8072 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1239,39 +1239,42 @@ opt_label:
 opt_property:
 	TOK_PROPERTY | /* empty */;
 
+opt_stmt_label:
+	TOK_ID ':' | /* empty */;
+
 assert:
-	TOK_ASSERT opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4));
+	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
 	} |
-	TOK_ASSUME opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
 	} |
-	TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
+	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
 	} |
-	TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
 	} |
-	TOK_COVER opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
+	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
 	} |
-	TOK_COVER opt_property '(' ')' ';' {
+	opt_stmt_label TOK_COVER opt_property '(' ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
 	} |
-	TOK_COVER ';' {
+	opt_stmt_label TOK_COVER ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
 	} |
-	TOK_RESTRICT opt_property '(' expr ')' ';' {
+	opt_stmt_label TOK_RESTRICT opt_property '(' expr ')' ';' {
 		if (norestrict_mode)
-			delete $4;
+			delete $5;
 		else
-			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
 	} |
-	TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+	opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode)
-			delete $5;
+			delete $6;
 		else
-			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
 	};
 
 assert_property:
-- 
cgit v1.2.3


From e060375f23d56b4e330a946d5a626f0163499618 Mon Sep 17 00:00:00 2001
From: Dan Gisselquist <zipcpu@gmail.com>
Date: Thu, 3 May 2018 12:35:01 +0200
Subject: Support more character literals

---
 frontends/verilog/verilog_lexer.l | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 32d7738cf..d12c9ee4e 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -241,10 +241,18 @@ YOSYS_NAMESPACE_END
 	while (yystr[i]) {
 		if (yystr[i] == '\\' && yystr[i + 1]) {
 			i++;
-			if (yystr[i] == 'n')
+			if (yystr[i] == 'a')
+				yystr[i] = '\a';
+			else if (yystr[i] == 'f')
+				yystr[i] = '\f';
+			else if (yystr[i] == 'n')
 				yystr[i] = '\n';
+			else if (yystr[i] == 'r')
+				yystr[i] = '\r';
 			else if (yystr[i] == 't')
 				yystr[i] = '\t';
+			else if (yystr[i] == 'v')
+				yystr[i] = '\v';
 			else if ('0' <= yystr[i] && yystr[i] <= '7') {
 				yystr[i] = yystr[i] - '0';
 				if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
-- 
cgit v1.2.3


From a572b495387743a58111e7264917a497faa17ebf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 3 May 2018 15:25:59 +0200
Subject: Replace -ignore_redef with -[no]overwrite

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_frontend.cc | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index e5917b97e..505c94619 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -137,9 +137,13 @@ struct VerilogFrontend : public Frontend {
 		log("    -icells\n");
 		log("        interpret cell types starting with '$' as internal cell types\n");
 		log("\n");
-		log("    -ignore_redef\n");
+		log("    -nooverwrite\n");
 		log("        ignore re-definitions of modules. (the default behavior is to\n");
-		log("        create an error message.)\n");
+		log("        create an error message if the existing module is not a black box\n");
+		log("        module, and overwrite the existing module otherwise.)\n");
+		log("\n");
+		log("    -overwrite\n");
+		log("        overwrite existing modules with the same name\n");
 		log("\n");
 		log("    -defer\n");
 		log("        only read the abstract syntax tree and defer actual compilation\n");
@@ -191,7 +195,8 @@ struct VerilogFrontend : public Frontend {
 		bool flag_nodpi = false;
 		bool flag_noopt = false;
 		bool flag_icells = false;
-		bool flag_ignore_redef = false;
+		bool flag_nooverwrite = false;
+		bool flag_overwrite = false;
 		bool flag_defer = false;
 		std::map<std::string, std::string> defines_map;
 		std::list<std::string> include_dirs;
@@ -289,8 +294,14 @@ struct VerilogFrontend : public Frontend {
 				flag_icells = true;
 				continue;
 			}
-			if (arg == "-ignore_redef") {
-				flag_ignore_redef = true;
+			if (arg == "-ignore_redef" || arg == "-nooverwrite") {
+				flag_nooverwrite = true;
+				flag_overwrite = false;
+				continue;
+			}
+			if (arg == "-overwrite") {
+				flag_nooverwrite = false;
+				flag_overwrite = true;
 				continue;
 			}
 			if (arg == "-defer") {
@@ -370,7 +381,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;
-- 
cgit v1.2.3


From 872d8d49e98fc5a4090ce20d902afbd0090c8c84 Mon Sep 17 00:00:00 2001
From: Jim Paris <jim@jtan.com>
Date: Thu, 17 May 2018 00:06:49 -0400
Subject: Skip spaces around macro arguments

---
 frontends/verilog/preproc.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index c43ff4e3a..00124cb42 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -244,6 +244,7 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
 				args.push_back(std::string());
 				while (1)
 				{
+					skip_spaces();
 					tok = next_token(true);
 					if (tok == ")" || tok == "}" || tok == "]")
 						level--;
-- 
cgit v1.2.3


From 4a229e5b953c15ecb31945258e0ca2f7bffe8a3e Mon Sep 17 00:00:00 2001
From: Jim Paris <jim@jtan.com>
Date: Thu, 17 May 2018 00:09:56 -0400
Subject: Support SystemVerilog `` extension for macros

---
 frontends/verilog/preproc.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 00124cb42..dea22ee8a 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false)
 		const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
 		if (ch == '`' || strchr(ok, ch) != NULL)
 		{
+			char first = ch;
 			ch = next_char();
-			if (ch == '"') {
+			if (first == '`' && (ch == '"' || ch == '`')) {
 				token += ch;
 			} else do {
 					if (strchr(ok, ch) == NULL) {
@@ -265,6 +266,9 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
 			}
 			insert_input(defines_map[name]);
 			return true;
+	} else if (tok == "``") {
+		// Swallow `` in macro expansion
+		return true;
 	} else return false;
 }
 
-- 
cgit v1.2.3


From 8b7580b0a152ec937abb1510abf5f2d7cd3b7acb Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Wed, 6 Jun 2018 22:27:25 +0300
Subject: Detect illegal port declaration, e.g input/output/inout keyword must
 be the first.

---
 frontends/verilog/verilog_parser.y | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e803d8072..72a501d11 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -376,9 +376,10 @@ wire_type:
 	};
 
 wire_type_token_list:
-	wire_type_token | wire_type_token_list wire_type_token;
+	wire_type_token | wire_type_token_list wire_type_token |
+	wire_type_token_io ;
 
-wire_type_token:
+wire_type_token_io:
 	TOK_INPUT {
 		astbuf3->is_input = true;
 	} |
@@ -388,7 +389,9 @@ wire_type_token:
 	TOK_INOUT {
 		astbuf3->is_input = true;
 		astbuf3->is_output = true;
-	} |
+	};
+
+wire_type_token:
 	TOK_WIRE {
 	} |
 	TOK_REG {
-- 
cgit v1.2.3


From b5ea598ef6cec535378c8cbb53170ccd1e5855ca Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 08:11:20 -0700
Subject: Use log_file_warning(), log_file_error() functions.

Wherever we can report a source-level location.
---
 frontends/verilog/verilog_frontend.cc | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 505c94619..be925fea2 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -42,7 +42,7 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
 static void error_on_dpi_function(AST::AstNode *node)
 {
 	if (node->type == AST::AST_DPI_FUNCTION)
-		log_error("Found DPI function %s at %s:%d.\n", node->str.c_str(), node->filename.c_str(), node->linenum);
+		log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str());
 	for (auto child : node->children)
 		error_on_dpi_function(child);
 }
@@ -519,13 +519,11 @@ void frontend_verilog_yyerror(char const *fmt, ...)
 	va_list ap;
 	char buffer[1024];
 	char *p = buffer;
-	p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
-			YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
 	va_start(ap, fmt);
 	p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
 	va_end(ap);
 	p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
-	YOSYS_NAMESPACE_PREFIX log_error("%s", buffer);
+	YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
+					      "%s", buffer);
 	exit(1);
 }
-
-- 
cgit v1.2.3


From 68b5d0c3b11588946982939c00fd6febe198e13f Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 09:37:44 -0700
Subject: Convert more log_error() to log_file_error() where possible.

Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
---
 frontends/verilog/const2ast.cc | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 4a58357bf..7848c626d 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -49,8 +49,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
 	int carry = 0;
 	for (size_t i = 0; i < digits.size(); i++) {
 		if (digits[i] >= 10)
-			log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n",
-				current_filename.c_str(), get_line_num());
+			log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
 		digits[i] += carry * 10;
 		carry = digits[i] % 2;
 		digits[i] /= 2;
@@ -105,8 +104,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 		int bits_per_digit = my_ilog2(base-1);
 		for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
 			if (*it > (base-1) && *it < 0xf0)
-				log_error("Digit larger than %d used in in base-%d constant at %s:%d.\n",
-					base-1, base, current_filename.c_str(), get_line_num());
+				log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n",
+					       base-1, base);
 			for (int i = 0; i < bits_per_digit; i++) {
 				int bitmask = 1 << i;
 				if (*it == 0xf0)
@@ -238,4 +237,3 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 }
 
 YOSYS_NAMESPACE_END
-
-- 
cgit v1.2.3


From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 frontends/verilog/verilog_frontend.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index be925fea2..911e36112 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -49,7 +49,7 @@ static void error_on_dpi_function(AST::AstNode *node)
 
 struct VerilogFrontend : public Frontend {
 	VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -180,7 +180,7 @@ struct VerilogFrontend : public Frontend {
 		log("supported by the Yosys Verilog front-end.\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
@@ -395,7 +395,7 @@ struct VerilogFrontend : public Frontend {
 
 struct VerilogDefaults : public Pass {
 	VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -416,7 +416,7 @@ struct VerilogDefaults : public Pass {
 		log("not imply -clear.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		if (args.size() < 2)
 			cmd_error(args, 1, "Missing argument.");
@@ -453,7 +453,7 @@ struct VerilogDefaults : public Pass {
 
 struct VerilogDefines : public Pass {
 	VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -469,7 +469,7 @@ struct VerilogDefines : public Pass {
 		log("        undefine the preprocessor symbol 'name'\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
-- 
cgit v1.2.3


From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Wed, 15 Aug 2018 19:56:30 +0300
Subject: A few minor enhancements to specify block parsing. Just remember
 specify blocks are parsed but ignored.

---
 frontends/verilog/verilog_parser.y | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 78cac5543..61da12b76 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -688,8 +688,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';'
-	// | full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value ';' |
+	full_path_description '=' path_delay_value ';'
 	;
 
 path_delay_value :
@@ -723,6 +723,17 @@ list_of_path_delay_expressions :
 parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
+full_path_description :
+	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+
+list_of_path_inputs :
+	specify_input_terminal_descriptor |
+	list_of_path_inputs ',' specify_input_terminal_descriptor ;
+	
+list_of_path_outputs :
+	specify_output_terminal_descriptor |
+	list_of_path_outputs ',' specify_output_terminal_descriptor ;
+	
 opt_polarity_operator :
 	'+'
 	| '-'
-- 
cgit v1.2.3


From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 00:08:08 +0300
Subject: Yosys can now parse
 https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v
 , (specify block ignored). Must use 'read_verilog -defer' due to a parameter
 not assigned a default value.

---
 frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 61da12b76..58a6824d1 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -654,7 +654,7 @@ specify_item:
 	// | pulsestyle_declaration
 	// | showcancelled_declaration
 	| path_declaration
-	// | system_timing_declaration
+	| system_timing_declaration
 	;
 
 specparam_declaration:
@@ -693,8 +693,8 @@ simple_path_declaration :
 	;
 
 path_delay_value :
-	//list_of_path_delay_expressions
-	'(' list_of_path_delay_expressions ')'
+	list_of_path_delay_expressions |
+	%prec '(' list_of_path_delay_expressions ')'
 	;
 
 list_of_path_delay_expressions :
@@ -724,12 +724,17 @@ parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
 
+// This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
-	specify_input_terminal_descriptor |
-	list_of_path_inputs ',' specify_input_terminal_descriptor ;
-	
+	specify_input_terminal_descriptor                  opt_polarity_operator  |
+	specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
+
+more_path_inputs :
+    ',' specify_input_terminal_descriptor |
+    more_path_inputs ',' specify_input_terminal_descriptor ;
+
 list_of_path_outputs :
 	specify_output_terminal_descriptor |
 	list_of_path_outputs ',' specify_output_terminal_descriptor ;
@@ -747,11 +752,18 @@ specify_input_terminal_descriptor :
 specify_output_terminal_descriptor :
 	TOK_ID ;
 
-/*
 system_timing_declaration :
-	;
-*/
+	TOK_ID '(' system_timing_args ')' ';' ;
+
+system_timing_arg :
+	TOK_POSEDGE TOK_ID |
+	TOK_NEGEDGE TOK_ID |
+	expr ;
 
+system_timing_args :
+	system_timing_arg |
+	system_timing_args ',' system_timing_arg ;
+ 
 /*
 t_path_delay_expression :
 	path_delay_expression;
-- 
cgit v1.2.3


From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 17:27:45 +0300
Subject: Fixed all known specify/endspecify issues, without breaking 'make
 test'. Some the of parser fixes may look strange but they were needed to
 avoid shift/reduce conflicts, due to the explicit parentheses in
 path_delay_value, and the mintypmax values without parentheses

---
 frontends/verilog/verilog_parser.y | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 58a6824d1..2389d7d31 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -682,22 +682,23 @@ showcancelled_declaration :
 */
 
 path_declaration :
-	simple_path_declaration
+	simple_path_declaration ';'
 	// | edge_sensitive_path_declaration
 	// | state_dependent_path_declaration
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';' |
-	full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value |
+	full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
-	list_of_path_delay_expressions |
-	%prec '(' list_of_path_delay_expressions ')'
+	'(' path_delay_expression list_of_path_delay_extra_expressions ')'
+	|     path_delay_expression
+	|     path_delay_expression list_of_path_delay_extra_expressions
 	;
 
-list_of_path_delay_expressions :
+list_of_path_delay_extra_expressions :
 /*
 	t_path_delay_expression
 	| trise_path_delay_expression ',' tfall_path_delay_expression
@@ -709,12 +710,11 @@ list_of_path_delay_expressions :
 	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
 	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
 */
-	path_delay_expression
-	| path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
@@ -815,7 +815,7 @@ tzx_path_delay_expression :
 */
 
 path_delay_expression :
-	constant_mintypmax_expression;
+	constant_expression;
 
 constant_mintypmax_expression :
 	constant_expression
-- 
cgit v1.2.3


From 042b3074f8096212b3f2114d353b2ec75818810b Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 23 Aug 2018 15:19:46 +0300
Subject: Added -no_dump_ptr flag for AST dump options in 'read_verilog' This
 option disables the memory pointer display. This is useful when diff'ing
 different dumps because otherwise the node pointers makes every diff line
 different when the AST content is the same.

---
 frontends/verilog/verilog_frontend.cc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 911e36112..8dcc7c5aa 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend {
 		log("    -dump_ast2\n");
 		log("        dump abstract syntax tree (after simplification)\n");
 		log("\n");
+		log("    -no_dump_ptr\n");
+		log("        do not include hex memory addresses in dump (easier to diff dumps)\n");
+		log("\n");
 		log("    -dump_vlog\n");
 		log("        dump ast as Verilog code (after simplification)\n");
 		log("\n");
@@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend {
 	{
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
+		bool flag_no_dump_ptr = false;
 		bool flag_dump_vlog = false;
 		bool flag_dump_rtlil = false;
 		bool flag_nolatches = false;
@@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend {
 				flag_dump_ast2 = true;
 				continue;
 			}
+			if (arg == "-no_dump_ptr") {
+				flag_no_dump_ptr = true;
+				continue;
+			}
 			if (arg == "-dump_vlog") {
 				flag_dump_vlog = true;
 				continue;
@@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;
-- 
cgit v1.2.3


From ddc1761f1a443ea9560c67cfc126160ba7254a39 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Aug 2018 14:22:21 +0200
Subject: Add "make coverage"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/.gitignore      | 2 +-
 frontends/verilog/Makefile.inc    | 7 +++----
 frontends/verilog/verilog_lexer.l | 2 +-
 3 files changed, 5 insertions(+), 6 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore
index 1d4ae9e5c..aadbcdcdd 100644
--- a/frontends/verilog/.gitignore
+++ b/frontends/verilog/.gitignore
@@ -1,4 +1,4 @@
 verilog_lexer.cc
 verilog_parser.output
 verilog_parser.tab.cc
-verilog_parser.tab.h
+verilog_parser.tab.hh
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index a06c1d5ab..dbaace585 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -1,15 +1,14 @@
 
 GENFILES += frontends/verilog/verilog_parser.tab.cc
-GENFILES += frontends/verilog/verilog_parser.tab.h
+GENFILES += frontends/verilog/verilog_parser.tab.hh
 GENFILES += frontends/verilog/verilog_parser.output
 GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $<
-	$(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc
+	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
-frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc
+frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
 frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
 	$(Q) mkdir -p $(dir $@)
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 0134416c1..83921bf0b 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -42,7 +42,7 @@
 #include "kernel/log.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "frontends/ast/ast.h"
-#include "verilog_parser.tab.h"
+#include "verilog_parser.tab.hh"
 
 USING_YOSYS_NAMESPACE
 using namespace AST;
-- 
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