From cd82ccd2581f93b17e2de017b7a2504d7733f2df Mon Sep 17 00:00:00 2001
From: huaixv <44743118+huaixv@users.noreply.github.com>
Date: Tue, 17 Mar 2020 13:00:12 +0800
Subject: Add precise locations for asserts

---
 frontends/verilog/verilog_parser.y | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 1132e97ae..54166fea7 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1955,6 +1955,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
+			SET_AST_NODE_LOC(node, @1, @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1967,6 +1968,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
+			SET_AST_NODE_LOC(node, @1, @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1979,6 +1981,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
+			SET_AST_NODE_LOC(node, @1, @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1991,6 +1994,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
+			SET_AST_NODE_LOC(node, @1, @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2000,6 +2004,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, $5);
+		SET_AST_NODE_LOC(node, @1, @6);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2008,6 +2013,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER opt_property '(' ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
+		SET_AST_NODE_LOC(node, @1, @5);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2016,6 +2022,7 @@ assert:
 	} |
 	opt_sva_label TOK_COVER ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
+		SET_AST_NODE_LOC(node, @1, @2);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
@@ -2027,6 +2034,7 @@ assert:
 			delete $5;
 		} else {
 			AstNode *node = new AstNode(AST_ASSUME, $5);
+			SET_AST_NODE_LOC(node, @1, @6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2041,6 +2049,7 @@ assert:
 			delete $6;
 		} else {
 			AstNode *node = new AstNode(AST_FAIR, $6);
+			SET_AST_NODE_LOC(node, @1, @7);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -2053,35 +2062,45 @@ assert:
 
 assert_property:
 	opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
+		AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
+		SET_AST_NODE_LOC(node, @1, @6);
+		ast_stack.back()->children.push_back(node);
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
 	opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+		AstNode *node = new AstNode(AST_ASSUME, $5);
+		SET_AST_NODE_LOC(node, @1, @6);
+		ast_stack.back()->children.push_back(node);
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
 	opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
+		AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
+		SET_AST_NODE_LOC(node, @1, @7);
+		ast_stack.back()->children.push_back(node);
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
 	opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+		AstNode *node = new AstNode(AST_FAIR, $6);
+		SET_AST_NODE_LOC(node, @1, @7);
+		ast_stack.back()->children.push_back(node);
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
 	opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
+		AstNode *node = new AstNode(AST_COVER, $5);
+		SET_AST_NODE_LOC(node, @1, @6);
+		ast_stack.back()->children.push_back(node);
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
@@ -2091,7 +2110,9 @@ assert_property:
 		if (norestrict_mode) {
 			delete $5;
 		} else {
-			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+			AstNode *node = new AstNode(AST_ASSUME, $5);
+			SET_AST_NODE_LOC(node, @1, @6);
+			ast_stack.back()->children.push_back(node);
 			if ($1 != nullptr) {
 				ast_stack.back()->children.back()->str = *$1;
 				delete $1;
@@ -2102,7 +2123,9 @@ assert_property:
 		if (norestrict_mode) {
 			delete $6;
 		} else {
-			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+			AstNode *node = new AstNode(AST_FAIR, $6);
+			SET_AST_NODE_LOC(node, @1, @7);
+			ast_stack.back()->children.push_back(node);
 			if ($1 != nullptr) {
 				ast_stack.back()->children.back()->str = *$1;
 				delete $1;
-- 
cgit v1.2.3


From dc75ed7dac9a203c8072b498e633e681ace58b6c Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 19 Mar 2020 16:53:40 +0100
Subject: Add one mode dependency

---
 frontends/verilog/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index 6a8462b41..cf9b9531e 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -10,7 +10,7 @@ frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 
 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
-frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
+frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l frontends/verilog/verilog_parser.tab.cc
 	$(Q) mkdir -p $(dir $@)
 	$(P) flex -o frontends/verilog/verilog_lexer.cc $<
 
-- 
cgit v1.2.3


From 14f32028ec878b8ba7324584631523f5b571b39f Mon Sep 17 00:00:00 2001
From: Peter <peter@crozier.com>
Date: Thu, 27 Feb 2020 16:57:35 +0000
Subject: Parser changes to support typedef.

---
 frontends/verilog/verilog_frontend.cc | 19 +++++++++++++++
 frontends/verilog/verilog_frontend.h  |  6 +++++
 frontends/verilog/verilog_lexer.l     | 28 ++++++++++++++++++++--
 frontends/verilog/verilog_parser.y    | 45 ++++++++++++++++++++++++++++-------
 4 files changed, 88 insertions(+), 10 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 42eabc02d..de05d29a7 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -47,6 +47,22 @@ static void error_on_dpi_function(AST::AstNode *node)
 		error_on_dpi_function(child);
 }
 
+static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
+{
+	// prime the parser's user type lookup table with the package qualified names
+	// of typedefed names in the packages seen so far.
+	user_types.clear();
+	for (const auto &pkg : package_list) {
+		log_assert(pkg->type==AST::AST_PACKAGE);
+		for (const auto &node: pkg->children) {
+			if (node->type == AST::AST_TYPEDEF) {
+				std::string s = pkg->str + "::" + node->str.substr(1);
+				user_types[s] = node;
+			}
+		}
+	}
+}
+
 struct VerilogFrontend : public Frontend {
 	VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
 	void help() YS_OVERRIDE
@@ -468,6 +484,9 @@ struct VerilogFrontend : public Frontend {
 		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
 				flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
+		// make latest package info available to next parser
+		add_package_types(pkg_user_types, design->verilog_packages);
+
 		if (!flag_nopp)
 			delete lexin;
 
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index a2e06f0e4..73ea51e6c 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -45,6 +45,12 @@ namespace VERILOG_FRONTEND
 	// this function converts a Verilog constant to an AST_CONSTANT node
 	AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
 
+	// names of locally typedef'ed types
+	extern std::map<std::string, AST::AstNode*> user_types;
+
+	// names of package typedef'ed types
+	extern std::map<std::string, AST::AstNode*> pkg_user_types;
+
 	// state of `default_nettype
 	extern bool default_nettype_wire;
 
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d22a18458..74e8dce7f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -372,9 +372,33 @@ supply1 { return TOK_SUPPLY1; }
 "$signed"   { return TOK_TO_SIGNED; }
 "$unsigned" { return TOK_TO_UNSIGNED; }
 
+[a-zA-Z_][a-zA-Z0-9_]*::[a-zA-Z_$][a-zA-Z0-9_$]* {
+	// package qualifier
+	auto s = std::string("\\") + yytext;
+	if (pkg_user_types.count(s) > 0) {
+		// found it
+		yylval->string = new std::string(s);
+		return TOK_USER_TYPE;
+	}
+	else {
+		// backup before :: just return first part
+		size_t len = strchr(yytext, ':') - yytext;
+		yyless(len);
+		yylval->string = new std::string(std::string("\\") + yytext);
+		return TOK_ID;
+	}
+}
+
 [a-zA-Z_$][a-zA-Z0-9_$]* {
-	yylval->string = new std::string(std::string("\\") + yytext);
-	return TOK_ID;
+	auto s = std::string("\\") + yytext;
+	if (user_types.count(s) > 0) {
+		yylval->string = new std::string(s);
+		return TOK_USER_TYPE;
+	}
+	else {
+		yylval->string = new std::string(std::string("\\") + yytext);
+		return TOK_ID;
+	}
 }
 
 [a-zA-Z_$][a-zA-Z0-9_$\.]* {
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e32682f18..690dfdb6e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -54,6 +54,8 @@ namespace VERILOG_FRONTEND {
 	std::map<std::string, AstNode*> *attr_list, default_attr_list;
 	std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
 	std::map<std::string, AstNode*> *albuf;
+	std::map<std::string, AstNode*> user_types;
+	std::map<std::string, AstNode*> pkg_user_types;
 	std::vector<AstNode*> ast_stack;
 	struct AstNode *astbuf1, *astbuf2, *astbuf3;
 	struct AstNode *current_function_or_task;
@@ -125,6 +127,26 @@ struct specify_rise_fall {
 	specify_triple fall;
 };
 
+static void addTypedefNode(std::string *name, AstNode *node)
+{
+	log_assert(node);
+	// seems to be support for local scoped typedefs in simplify()
+	// and tests redefine types.
+	//if (user_types.count(*name) > 0) {
+	//	frontend_verilog_yyerror("Type already defined.");
+	//}
+	auto *tnode = new AstNode(AST_TYPEDEF, node);
+	tnode->str = *name;
+	user_types[*name] = tnode;
+	if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
+		// typedef inside a package so we need the qualified name
+		auto qname = current_ast_mod->str + "::" + (*name).substr(1);
+		pkg_user_types[qname] = tnode;
+	}
+	delete name;
+	ast_stack.back()->children.push_back(tnode);
+}
+
 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
 {
 	auto range = new AstNode(AST_RANGE);
@@ -167,6 +189,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
+%token <string> TOK_USER_TYPE
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -190,6 +213,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
+%type <string> type_name
 %type <ast> opt_enum_init
 %type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
 %type <al> attr case_attr
@@ -330,7 +354,9 @@ hierarchical_id:
 	};
 
 hierarchical_type_id:
-	'(' hierarchical_id ')' { $$ = $2; };
+	TOK_USER_TYPE
+	| '(' TOK_USER_TYPE ')'	{ $$ = $2; }		// non-standard grammar
+	;
 
 module:
 	attr TOK_MODULE TOK_ID {
@@ -352,6 +378,7 @@ module:
 		ast_stack.pop_back();
 		log_assert(ast_stack.size() == 1);
 		current_ast_mod = NULL;
+		user_types.clear();
 	};
 
 module_para_opt:
@@ -465,6 +492,7 @@ package:
 	} ';' package_body TOK_ENDPACKAGE {
 		ast_stack.pop_back();
 		current_ast_mod = NULL;
+		user_types.clear();
 	};
 
 package_body:
@@ -1591,8 +1619,12 @@ assign_expr:
 		ast_stack.back()->children.push_back(node);
 	};
 
+type_name: TOK_ID		// first time seen
+	 | TOK_USER_TYPE	// redefinition
+	 ;
+
 typedef_decl:
-	TOK_TYPEDEF wire_type range TOK_ID range_or_multirange ';' {
+	TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
 		astbuf1 = $2;
 		astbuf2 = $3;
 		if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
@@ -1625,13 +1657,10 @@ typedef_decl:
 			}
 			astbuf1->children.push_back(rangeNode);
 		}
-
-		ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1));
-		ast_stack.back()->children.back()->str = *$4;
+		addTypedefNode($4, astbuf1);
 	} |
-	TOK_TYPEDEF enum_type TOK_ID ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1));
-		ast_stack.back()->children.back()->str = *$3;
+	TOK_TYPEDEF enum_type type_name ';' {
+		addTypedefNode($3, astbuf1);
 	}
 	;
 
-- 
cgit v1.2.3


From 0aaa36ca6d4a95771ef26a515b64031c4d43be11 Mon Sep 17 00:00:00 2001
From: Peter <peter@crozier.com>
Date: Tue, 3 Mar 2020 19:30:54 +0000
Subject: Clear pkg_user_types if no packages following a 'design -reset-vlog'.

---
 frontends/verilog/verilog_frontend.cc | 4 ++++
 frontends/verilog/verilog_parser.y    | 1 +
 2 files changed, 5 insertions(+)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index de05d29a7..61db0a176 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -465,6 +465,10 @@ struct VerilogFrontend : public Frontend {
 				log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
 			lexin = new std::istringstream(code_after_preproc);
 		}
+		if (design->verilog_packages.empty()) {
+			// might be because of a `design -reset-vlog` command
+			pkg_user_types.clear();
+		}
 
 		frontend_verilog_yyset_lineno(1);
 		frontend_verilog_yyrestart(NULL);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 690dfdb6e..f7e3afd13 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -522,6 +522,7 @@ interface:
 		ast_stack.pop_back();
 		log_assert(ast_stack.size() == 1);
 		current_ast_mod = NULL;
+		user_types.clear();
 	};
 
 interface_body:
-- 
cgit v1.2.3


From c06eda25041cd567ac53da52d486dfd0daa8eaff Mon Sep 17 00:00:00 2001
From: Peter Crozier <peter@crozier.com>
Date: Sun, 15 Mar 2020 19:01:46 +0000
Subject: Build pkg_user_types before parsing in case of changes in the design.

---
 frontends/verilog/verilog_frontend.cc | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 61db0a176..f2c1c227f 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -465,10 +465,9 @@ struct VerilogFrontend : public Frontend {
 				log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
 			lexin = new std::istringstream(code_after_preproc);
 		}
-		if (design->verilog_packages.empty()) {
-			// might be because of a `design -reset-vlog` command
-			pkg_user_types.clear();
-		}
+
+		// make package typedefs available to parser
+		add_package_types(pkg_user_types, design->verilog_packages);
 
 		frontend_verilog_yyset_lineno(1);
 		frontend_verilog_yyrestart(NULL);
@@ -488,8 +487,6 @@ struct VerilogFrontend : public Frontend {
 		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
 				flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
-		// make latest package info available to next parser
-		add_package_types(pkg_user_types, design->verilog_packages);
 
 		if (!flag_nopp)
 			delete lexin;
-- 
cgit v1.2.3


From ecc22f7fedfa639482dbc55a05709da85116a60f Mon Sep 17 00:00:00 2001
From: Peter Crozier <peter@crozier.com>
Date: Mon, 23 Mar 2020 20:07:22 +0000
Subject: Support module/package/interface/block scope for typedef names.

---
 frontends/verilog/verilog_frontend.cc |  3 ++-
 frontends/verilog/verilog_frontend.h  |  5 ++--
 frontends/verilog/verilog_lexer.l     | 17 ++++++++++--
 frontends/verilog/verilog_parser.y    | 51 ++++++++++++++++++++++++-----------
 4 files changed, 56 insertions(+), 20 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index f2c1c227f..1c88d479b 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -51,7 +51,6 @@ static void add_package_types(std::map<std::string, AST::AstNode *> &user_types,
 {
 	// prime the parser's user type lookup table with the package qualified names
 	// of typedefed names in the packages seen so far.
-	user_types.clear();
 	for (const auto &pkg : package_list) {
 		log_assert(pkg->type==AST::AST_PACKAGE);
 		for (const auto &node: pkg->children) {
@@ -61,6 +60,8 @@ static void add_package_types(std::map<std::string, AST::AstNode *> &user_types,
 			}
 		}
 	}
+	user_type_stack.clear();
+	user_type_stack.push_back(new UserTypeMap());
 }
 
 struct VerilogFrontend : public Frontend {
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 73ea51e6c..caa6246ef 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -45,8 +45,9 @@ namespace VERILOG_FRONTEND
 	// this function converts a Verilog constant to an AST_CONSTANT node
 	AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
 
-	// names of locally typedef'ed types
-	extern std::map<std::string, AST::AstNode*> user_types;
+	// names of locally typedef'ed types in a stack
+	typedef std::map<std::string, AST::AstNode*> UserTypeMap;
+	extern std::vector<UserTypeMap *> user_type_stack;
 
 	// names of package typedef'ed types
 	extern std::map<std::string, AST::AstNode*> pkg_user_types;
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 74e8dce7f..bccdf4841 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -99,6 +99,18 @@ YYLTYPE old_location;
 #define YY_BUF_SIZE 65536
 
 extern int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
+
+static bool isUserType(std::string &s)
+{
+	// check current scope then outer scopes for a name
+	for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {
+		if ((*it)->count(s) > 0) {
+			return true;
+		}
+	}
+	return false;
+}
+
 %}
 
 %option yylineno
@@ -376,7 +388,7 @@ supply1 { return TOK_SUPPLY1; }
 	// package qualifier
 	auto s = std::string("\\") + yytext;
 	if (pkg_user_types.count(s) > 0) {
-		// found it
+		// package qualified typedefed name
 		yylval->string = new std::string(s);
 		return TOK_USER_TYPE;
 	}
@@ -391,7 +403,8 @@ supply1 { return TOK_SUPPLY1; }
 
 [a-zA-Z_$][a-zA-Z0-9_$]* {
 	auto s = std::string("\\") + yytext;
-	if (user_types.count(s) > 0) {
+	if (isUserType(s)) {
+		// previously typedefed name
 		yylval->string = new std::string(s);
 		return TOK_USER_TYPE;
 	}
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f7e3afd13..1a195bbfd 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -54,7 +54,7 @@ namespace VERILOG_FRONTEND {
 	std::map<std::string, AstNode*> *attr_list, default_attr_list;
 	std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
 	std::map<std::string, AstNode*> *albuf;
-	std::map<std::string, AstNode*> user_types;
+	std::vector<UserTypeMap*> user_type_stack;
 	std::map<std::string, AstNode*> pkg_user_types;
 	std::vector<AstNode*> ast_stack;
 	struct AstNode *astbuf1, *astbuf2, *astbuf3;
@@ -130,14 +130,10 @@ struct specify_rise_fall {
 static void addTypedefNode(std::string *name, AstNode *node)
 {
 	log_assert(node);
-	// seems to be support for local scoped typedefs in simplify()
-	// and tests redefine types.
-	//if (user_types.count(*name) > 0) {
-	//	frontend_verilog_yyerror("Type already defined.");
-	//}
 	auto *tnode = new AstNode(AST_TYPEDEF, node);
 	tnode->str = *name;
-	user_types[*name] = tnode;
+	auto user_types = user_type_stack.back();
+	(*user_types)[*name] = tnode;
 	if (current_ast_mod && current_ast_mod->type == AST_PACKAGE) {
 		// typedef inside a package so we need the qualified name
 		auto qname = current_ast_mod->str + "::" + (*name).substr(1);
@@ -147,6 +143,17 @@ static void addTypedefNode(std::string *name, AstNode *node)
 	ast_stack.back()->children.push_back(tnode);
 }
 
+static void enterTypeScope()
+{
+	auto user_types = new UserTypeMap();
+	user_type_stack.push_back(user_types);
+}
+
+static void exitTypeScope()
+{
+	user_type_stack.pop_back();
+}
+
 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
 {
 	auto range = new AstNode(AST_RANGE);
@@ -359,7 +366,7 @@ hierarchical_type_id:
 	;
 
 module:
-	attr TOK_MODULE TOK_ID {
+	attr module_start TOK_ID {
 		do_not_require_port_stubs = false;
 		AstNode *mod = new AstNode(AST_MODULE);
 		ast_stack.back()->children.push_back(mod);
@@ -378,9 +385,12 @@ module:
 		ast_stack.pop_back();
 		log_assert(ast_stack.size() == 1);
 		current_ast_mod = NULL;
-		user_types.clear();
+		exitTypeScope();
 	};
 
+module_start: TOK_MODULE	{ enterTypeScope(); }
+	;
+
 module_para_opt:
 	'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
 
@@ -482,7 +492,7 @@ module_arg:
 	};
 
 package:
-	attr TOK_PACKAGE TOK_ID {
+	attr package_start TOK_ID {
 		AstNode *mod = new AstNode(AST_PACKAGE);
 		ast_stack.back()->children.push_back(mod);
 		ast_stack.push_back(mod);
@@ -492,9 +502,12 @@ package:
 	} ';' package_body TOK_ENDPACKAGE {
 		ast_stack.pop_back();
 		current_ast_mod = NULL;
-		user_types.clear();
+		exitTypeScope();
 	};
 
+package_start: TOK_PACKAGE	{ enterTypeScope(); }
+	;
+
 package_body:
 	package_body package_body_stmt
 	| // optional
@@ -505,7 +518,7 @@ package_body_stmt:
 	localparam_decl;
 
 interface:
-	TOK_INTERFACE TOK_ID {
+	interface_start TOK_ID {
 		do_not_require_port_stubs = false;
 		AstNode *intf = new AstNode(AST_INTERFACE);
 		ast_stack.back()->children.push_back(intf);
@@ -522,9 +535,12 @@ interface:
 		ast_stack.pop_back();
 		log_assert(ast_stack.size() == 1);
 		current_ast_mod = NULL;
-		user_types.clear();
+		exitTypeScope();
 	};
 
+interface_start: TOK_INTERFACE	{ enterTypeScope(); }
+	;
+
 interface_body:
 	interface_body interface_body_stmt |;
 
@@ -2210,7 +2226,7 @@ behavioral_stmt:
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
-	attr TOK_BEGIN opt_label {
+	attr begin opt_label {
 		AstNode *node = new AstNode(AST_BLOCK);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
@@ -2218,6 +2234,7 @@ behavioral_stmt:
 		if ($3 != NULL)
 			node->str = *$3;
 	} behavioral_stmt_list TOK_END opt_label {
+		exitTypeScope();
 		if ($3 != NULL && $7 != NULL && *$3 != *$7)
 			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
 		if ($3 != NULL)
@@ -2301,6 +2318,9 @@ behavioral_stmt:
 		ast_stack.pop_back();
 	};
 
+begin: TOK_BEGIN	{ enterTypeScope(); }
+	;
+
 unique_case_attr:
 	/* empty */ {
 		$$ = false;
@@ -2516,12 +2536,13 @@ gen_stmt:
 		case_type_stack.pop_back();
 		ast_stack.pop_back();
 	} |
-	TOK_BEGIN opt_label {
+	begin opt_label {
 		AstNode *node = new AstNode(AST_GENBLOCK);
 		node->str = $2 ? *$2 : std::string();
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} module_gen_body TOK_END opt_label {
+		exitTypeScope();
 		if ($2 != NULL)
 			delete $2;
 		if ($6 != NULL)
-- 
cgit v1.2.3


From 9a8a644ad11e6fd95b6a1800e357e9cf282f5275 Mon Sep 17 00:00:00 2001
From: Peter Crozier <peter@crozier.com>
Date: Tue, 24 Mar 2020 14:35:21 +0000
Subject: Error duplicate declarations of a typedef name in the same scope.

---
 frontends/verilog/verilog_lexer.l  |  2 +-
 frontends/verilog/verilog_parser.y | 12 ++++++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index bccdf4841..f6a3ac4db 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -390,7 +390,7 @@ supply1 { return TOK_SUPPLY1; }
 	if (pkg_user_types.count(s) > 0) {
 		// package qualified typedefed name
 		yylval->string = new std::string(s);
-		return TOK_USER_TYPE;
+		return TOK_PKG_USER_TYPE;
 	}
 	else {
 		// backup before :: just return first part
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 1a195bbfd..d31740c6a 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -154,6 +154,13 @@ static void exitTypeScope()
 	user_type_stack.pop_back();
 }
 
+static bool isInLocalScope(const std::string *name)
+{
+	// tests if a name was declared in the current block scope
+	auto user_types = user_type_stack.back();
+	return (user_types->count(*name) > 0);
+}
+
 static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
 {
 	auto range = new AstNode(AST_RANGE);
@@ -196,7 +203,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS
 %token <string> TOK_BASE TOK_BASED_CONSTVAL TOK_UNBASED_UNSIZED_CONSTVAL
-%token <string> TOK_USER_TYPE
+%token <string> TOK_USER_TYPE TOK_PKG_USER_TYPE
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -362,6 +369,7 @@ hierarchical_id:
 
 hierarchical_type_id:
 	TOK_USER_TYPE
+	| TOK_PKG_USER_TYPE				// package qualified type name
 	| '(' TOK_USER_TYPE ')'	{ $$ = $2; }		// non-standard grammar
 	;
 
@@ -1637,7 +1645,7 @@ assign_expr:
 	};
 
 type_name: TOK_ID		// first time seen
-	 | TOK_USER_TYPE	// redefinition
+	 | TOK_USER_TYPE	{ if (isInLocalScope($1)) frontend_verilog_yyerror("Duplicate declaration of TYPEDEF '%s'", $1->c_str()+1); }
 	 ;
 
 typedef_decl:
-- 
cgit v1.2.3


From 044ca9dde409e3c91542fe95513d6641110f8462 Mon Sep 17 00:00:00 2001
From: Rupert Swarbrick <rswarbrick@lowrisc.org>
Date: Tue, 17 Mar 2020 09:34:31 +0000
Subject: Add support for SystemVerilog-style `define to Verilog frontend

This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
---
 frontends/verilog/preproc.cc          | 620 ++++++++++++++++++++++++++--------
 frontends/verilog/preproc.h           |  77 +++++
 frontends/verilog/verilog_frontend.cc |  26 +-
 frontends/verilog/verilog_frontend.h  |   4 -
 4 files changed, 578 insertions(+), 149 deletions(-)
 create mode 100644 frontends/verilog/preproc.h

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 161253a99..7905ea598 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -32,8 +32,10 @@
  *
  */
 
+#include "preproc.h"
 #include "verilog_frontend.h"
 #include "kernel/log.h"
+#include <assert.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
@@ -199,6 +201,175 @@ static std::string next_token(bool pass_newline = false)
 	return token;
 }
 
+struct macro_arg_t
+{
+	macro_arg_t(const std::string &name_, const char *default_value_)
+		: name(name_),
+		  has_default(default_value_ != nullptr),
+		  default_value(default_value_ ? default_value_ : "")
+	{}
+
+	std::string name;
+	bool        has_default;
+	std::string default_value;
+};
+
+static bool all_white(const std::string &str)
+{
+	for (char c : str)
+		if (!isspace(c))
+			return false;
+	return true;
+}
+
+struct arg_map_t
+{
+	arg_map_t()
+	{}
+
+	void add_arg(const std::string &name, const char *default_value)
+	{
+		if (find(name)) {
+			log_error("Duplicate macro arguments with name `%s'.\n", name.c_str());
+		}
+
+		name_to_pos[name] = args.size();
+		args.push_back(macro_arg_t(name, default_value));
+	}
+
+	// Find an argument by name; return nullptr if it doesn't exist. If pos is not null, write
+	// the argument's position to it on success.
+	const macro_arg_t *find(const std::string &name, int *pos = nullptr) const
+	{
+		auto it = name_to_pos.find(name);
+		if (it == name_to_pos.end())
+			return nullptr;
+
+		if (pos) *pos = it->second;
+		return &args[it->second];
+	}
+
+	// Construct the name for the local macro definition we use for the given argument
+	// (something like macro_foobar_arg2). This doesn't include the leading backtick.
+	static std::string str_token(const std::string &macro_name, int pos)
+	{
+		return stringf("macro_%s_arg%d", macro_name.c_str(), pos);
+	}
+
+	// Return definitions for the macro arguments (so that substituting in the macro body and
+	// then performing macro expansion will do argument substitution properly).
+	std::vector<std::pair<std::string, std::string>>
+	get_vals(const std::string &macro_name, const std::vector<std::string> &arg_vals) const
+	{
+		std::vector<std::pair<std::string, std::string>> ret;
+		for (int i = 0; i < GetSize(args); ++ i) {
+			// The SystemVerilog rules are:
+			//
+			//   - If the call site specifies an argument and it's not whitespace, use
+			//     it.
+			//
+			//   - Otherwise, if the argument has a default value, use it.
+			//
+			//   - Otherwise, if the call site specified whitespace, use that.
+			//
+			//   - Otherwise, error.
+			const std::string *dflt = nullptr;
+			if (args[i].has_default)
+				dflt = &args[i].default_value;
+
+			const std::string *given = nullptr;
+			if (i < GetSize(arg_vals))
+				given = &arg_vals[i];
+
+			const std::string *val = nullptr;
+			if (given && (! (dflt && all_white(*given))))
+				val = given;
+			else if (dflt)
+				val = dflt;
+			else if (given)
+				val = given;
+			else
+				log_error("Cannot expand macro `%s by giving only %d argument%s "
+				          "(argument %d has no default).\n",
+				          macro_name.c_str(), GetSize(arg_vals),
+				          (GetSize(arg_vals) == 1 ? "" : "s"), i + 1);
+
+			assert(val);
+			ret.push_back(std::make_pair(str_token(macro_name, i), * val));
+		}
+		return ret;
+	}
+
+
+	std::vector<macro_arg_t>   args;
+	std::map<std::string, int> name_to_pos;
+};
+
+struct define_body_t
+{
+	define_body_t(const std::string &body, const arg_map_t *args = nullptr)
+	  : body(body),
+	    has_args(args != nullptr),
+	    args(args ? *args : arg_map_t())
+	{}
+
+	std::string body;
+	bool        has_args;
+	arg_map_t   args;
+};
+
+define_map_t::define_map_t()
+{
+	add("YOSYS", "1");
+	add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
+}
+
+// We must define this destructor here (rather than relying on the default), because we need to
+// define it somewhere we've got a complete definition of define_body_t.
+define_map_t::~define_map_t()
+{}
+
+void
+define_map_t::add(const std::string &name, const std::string &txt, const arg_map_t *args)
+{
+	defines[name] = std::unique_ptr<define_body_t>(new define_body_t(txt, args));
+}
+
+void define_map_t::merge(const define_map_t &map)
+{
+	for (const auto &pr : map.defines) {
+		// These contortions are so that we take a copy of each definition body in
+		// map.defines.
+		defines[pr.first] = std::unique_ptr<define_body_t>(new define_body_t(*pr.second));
+	}
+}
+
+const define_body_t *define_map_t::find(const std::string &name) const
+{
+	auto it = defines.find(name);
+	return (it == defines.end()) ? nullptr : it->second.get();
+}
+
+void define_map_t::erase(const std::string &name)
+{
+	defines.erase(name);
+}
+
+void define_map_t::clear()
+{
+	defines.clear();
+}
+
+void define_map_t::log() const
+{
+	for (auto &it : defines) {
+		const std::string &name = it.first;
+		const define_body_t &body = *it.second;
+		Yosys::log("`define %s%s %s\n",
+		           name.c_str(), body.has_args ? "()" : "", body.body.c_str());
+	}
+}
+
 static void input_file(std::istream &f, std::string filename)
 {
 	char buffer[513];
@@ -215,11 +386,59 @@ static void input_file(std::istream &f, std::string filename)
 	input_buffer.insert(it, "\n`file_pop\n");
 }
 
+// Read tokens to get one argument (either a macro argument at a callsite or a default argument in a
+// macro definition). Writes the argument to dest. Returns true if we finished with ')' (the end of
+// the argument list); false if we finished with ','.
+static bool read_argument(std::string &dest)
+{
+	std::vector<char> openers;
+	for (;;) {
+		skip_spaces();
+		std::string tok = next_token(true);
+		if (tok == ")") {
+			if (openers.empty())
+				return true;
+			if (openers.back() != '(')
+				log_error("Mismatched brackets in macro argument: %c and %c.\n",
+				          openers.back(), tok[0]);
+
+			openers.pop_back();
+			dest += tok;
+			continue;
+		}
+		if (tok == "]") {
+			char opener = openers.empty() ? '(' : openers.back();
+			if (opener != '[')
+				log_error("Mismatched brackets in macro argument: %c and %c.\n",
+				          opener, tok[0]);
+
+			openers.pop_back();
+			dest += tok;
+			continue;
+		}
+		if (tok == "}") {
+			char opener = openers.empty() ? '(' : openers.back();
+			if (opener != '{')
+				log_error("Mismatched brackets in macro argument: %c and %c.\n",
+				          opener, tok[0]);
+
+			openers.pop_back();
+			dest += tok;
+			continue;
+		}
+
+		if (tok == "," && openers.empty()) {
+			return false;
+		}
+
+		if (tok == "(" || tok == "[" || tok == "{")
+			openers.push_back(tok[0]);
 
-static bool try_expand_macro(std::set<std::string> &defines_with_args,
-			     std::map<std::string, std::string> &defines_map,
-			     std::string &tok
-				    )
+		dest += tok;
+	}
+}
+
+static bool try_expand_macro(define_map_t &defines, std::string &tok)
 {
 	if (tok == "`\"") {
 		std::string literal("\"");
@@ -229,54 +448,272 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
 			if (ntok == "`\"") {
 				insert_input(literal+"\"");
 				return true;
-			} else if (!try_expand_macro(defines_with_args, defines_map, ntok)) {
+			} else if (!try_expand_macro(defines, ntok)) {
 					literal += ntok;
 			}
 		}
 		return false; // error - unmatched `"
-	} else if (tok.size() > 1 && tok[0] == '`' && defines_map.count(tok.substr(1)) > 0) {
-			std::string name = tok.substr(1);
-			// printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str());
-			std::string skipped_spaces = skip_spaces();
-			tok = next_token(false);
-			if (tok == "(" && defines_with_args.count(name) > 0) {
-				int level = 1;
-				std::vector<std::string> args;
-				args.push_back(std::string());
-				while (1)
-				{
-					skip_spaces();
-					tok = next_token(true);
-					if (tok == ")" || tok == "}" || tok == "]")
-						level--;
-					if (level == 0)
-						break;
-					if (level == 1 && tok == ",")
-						args.push_back(std::string());
-					else
-						args.back() += tok;
-					if (tok == "(" || tok == "{" || tok == "[")
-						level++;
-				}
-				for (int i = 0; i < GetSize(args); i++)
-					defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i];
-			} else {
-				insert_input(tok);
-				insert_input(skipped_spaces);
-			}
-			insert_input(defines_map[name]);
-			return true;
-	} else if (tok == "``") {
+	}
+
+	if (tok == "``") {
 		// Swallow `` in macro expansion
 		return true;
-	} else return false;
+	}
+
+	if (tok.size() <= 1 || tok[0] != '`')
+		return false;
+
+	// This token looks like a macro name (`foo).
+	std::string macro_name = tok.substr(1);
+	const define_body_t *body = defines.find(tok.substr(1));
+
+	if (! body) {
+		// Apparently not a name we know.
+		return false;
+	}
+
+	std::string name = tok.substr(1);
+	std::string skipped_spaces = skip_spaces();
+	tok = next_token(false);
+	if (tok == "(" && body->has_args) {
+		std::vector<std::string> args;
+		bool done = false;
+		while (!done) {
+			std::string arg;
+			done = read_argument(arg);
+			args.push_back(arg);
+		}
+		for (const auto &pr : body->args.get_vals(name, args)) {
+			defines.add(pr.first, pr.second);
+		}
+	} else {
+		insert_input(tok);
+		insert_input(skipped_spaces);
+	}
+	insert_input(body->body);
+	return true;
 }
 
-std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map,
-		dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs)
+// Read the arguments for a `define preprocessor directive with formal arguments. This is called
+// just after reading the token containing "(". Returns the number of newlines to emit afterwards to
+// keep line numbers in sync, together with the map from argument name to data (pos and default
+// value).
+static std::pair<int, arg_map_t>
+read_define_args()
 {
-	std::set<std::string> defines_with_args;
-	std::map<std::string, std::string> defines_map(pre_defines_map);
+	// Each argument looks like one of the following:
+	//
+	//     identifier
+	//     identifier = default_text
+	//     identifier =
+	//
+	// The first example is an argument with no default value. The second is an argument whose
+	// default value is default_text. The third is an argument with default value the empty
+	// string.
+
+	int newline_count = 0;
+	arg_map_t args;
+
+	// FSM state.
+	//
+	//   0: At start of identifier
+	//   1: After identifier (stored in arg_name)
+	//   2: After closing paren
+	int state = 0;
+
+	std::string arg_name, default_val;
+
+	skip_spaces();
+	for (;;) {
+		if (state == 2)
+			// We've read the closing paren.
+			break;
+
+		std::string tok = next_token();
+
+		// Cope with escaped EOLs
+		if (tok == "\\") {
+			char ch = next_char();
+			if (ch == '\n') {
+				// Eat the \, the \n and any trailing space and keep going.
+				skip_spaces();
+				continue;
+			} else {
+				// There aren't any other situations where a backslash makes sense.
+				log_error("Backslash in macro arguments (not at end of line).\n");
+			}
+		}
+
+		switch (state) {
+		case 0:
+			// At start of argument. If the token is ')', we've presumably just seen
+			// something like "`define foo() ...". Set state to 2 to finish. Otherwise,
+			// the token should be a valid simple identifier, but we'll allow anything
+			// here.
+			if (tok == ")") {
+				state = 2;
+			} else {
+				arg_name = tok;
+				state = 1;
+			}
+			skip_spaces();
+			break;
+
+		case 1:
+			// After argument. The token should either be an equals sign or a comma or
+			// closing paren.
+			if (tok == "=") {
+				std::string default_val;
+				//Read an argument into default_val and set state to 2 if we're at
+				// the end; 0 if we hit a comma.
+				state = read_argument(default_val) ? 2 : 0;
+				args.add_arg(arg_name, default_val.c_str());
+				skip_spaces();
+				break;
+			}
+			if (tok == ",") {
+				// Take the identifier as an argument with no default value.
+				args.add_arg(arg_name, nullptr);
+				state = 0;
+				skip_spaces();
+				break;
+			}
+			if (tok == ")") {
+				// As with comma, but set state to 2 (end of args)
+				args.add_arg(arg_name, nullptr);
+				state = 2;
+				skip_spaces();
+				break;
+			}
+			log_error("Trailing contents after identifier in macro argument `%s': "
+				  "expected '=', ',' or ')'.\n",
+				  arg_name.c_str());
+
+		default:
+			// The only FSM states are 0-2 and we dealt with 2 at the start of the loop.
+			__builtin_unreachable();
+		}
+	}
+
+	return std::make_pair(newline_count, args);
+}
+
+// Read a `define preprocessor directive. This is called just after reading the token containing
+// "`define".
+static void
+read_define(const std::string &filename,
+            define_map_t      &defines_map,
+            define_map_t      &global_defines_cache)
+{
+	std::string name, value;
+	arg_map_t args;
+
+	skip_spaces();
+	name = next_token(true);
+
+	bool here_doc_mode = false;
+	int newline_count = 0;
+
+	// The FSM state starts at 0. If it sees space (or enters here_doc_mode), it assumes this is
+	// a macro without formal arguments and jumps to state 1.
+	//
+	// In state 0, if it sees an opening parenthesis, it assumes this is a macro with formal
+	// arguments. It reads the arguments with read_define_args() and then jumps to state 2.
+	//
+	// In states 1 or 2, the FSM reads tokens to the end of line (or end of here_doc): this is
+	// the body of the macro definition.
+	int state = 0;
+
+	if (skip_spaces() != "")
+		state = 1;
+
+	for (;;) {
+		std::string tok = next_token();
+		if (tok.empty())
+			break;
+
+		// printf("define-tok: >>%s<<\n", tok != "\n" ? tok.c_str() : "NEWLINE");
+
+		if (tok == "\"\"\"") {
+			here_doc_mode = !here_doc_mode;
+			continue;
+		}
+
+		if (state == 0 && tok == "(") {
+			auto pr = read_define_args();
+			newline_count += pr.first;
+			args = pr.second;
+
+			state = 2;
+			continue;
+		}
+
+		// This token isn't an opening parenthesis immediately following the macro name, so
+		// it's presumably at or after the start of the macro body. If state isn't already 2
+		// (which would mean we'd parsed an argument list), set it to 1.
+		if (state == 0) {
+			state = 1;
+		}
+
+		if (tok == "\n") {
+			if (here_doc_mode) {
+				value += " ";
+				newline_count++;
+			} else {
+				return_char('\n');
+				break;
+			}
+			continue;
+		}
+
+		if (tok == "\\") {
+			char ch = next_char();
+			if (ch == '\n') {
+				value += " ";
+				newline_count++;
+			} else {
+				value += std::string("\\");
+				return_char(ch);
+			}
+			continue;
+		}
+
+		// Is this token the name of a macro argument? If so, replace it with a magic symbol
+		// that we'll replace with the argument value.
+		int arg_pos;
+		if (args.find(tok, &arg_pos)) {
+			value += '`' + args.str_token(name, arg_pos);
+			continue;
+		}
+
+		// This token is nothing special. Insert it verbatim into the macro body.
+		value += tok;
+	}
+
+	// Append some newlines so that we don't mess up line counts in error messages.
+	while (newline_count-- > 0)
+		return_char('\n');
+
+	if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) {
+		// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
+		defines_map.add(name, value, (state == 2) ? &args : nullptr);
+		global_defines_cache.add(name, value, (state == 2) ? &args : nullptr);
+	} else {
+		log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str());
+	}
+}
+
+std::string
+frontend_verilog_preproc(std::istream                 &f,
+                         std::string                   filename,
+                         const define_map_t           &pre_defines,
+                         define_map_t                 &global_defines_cache,
+                         const std::list<std::string> &include_dirs)
+{
+	define_map_t defines;
+	defines.merge(pre_defines);
+	defines.merge(global_defines_cache);
+
 	std::vector<std::string> filename_stack;
 	int ifdef_fail_level = 0;
 	bool in_elseif = false;
@@ -287,18 +724,6 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 
 	input_file(f, filename);
 
-	defines_map["YOSYS"] = "1";
-	defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1";
-
-	for (auto &it : pre_defines_map)
-		defines_map[it.first] = it.second;
-
-	for (auto &it : global_defines_cache) {
-		if (it.second.second)
-			defines_with_args.insert(it.first);
-		defines_map[it.first] = it.second.first;
-	}
-
 	while (!input_buffer.empty())
 	{
 		std::string tok = next_token();
@@ -325,7 +750,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 			std::string name = next_token(true);
 			if (ifdef_fail_level == 0)
 				ifdef_fail_level = 1, in_elseif = true;
-			else if (ifdef_fail_level == 1 && defines_map.count(name) != 0)
+			else if (ifdef_fail_level == 1 && defines.find(name))
 				ifdef_fail_level = 0, in_elseif = true;
 			continue;
 		}
@@ -333,7 +758,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 		if (tok == "`ifdef") {
 			skip_spaces();
 			std::string name = next_token(true);
-			if (ifdef_fail_level > 0 || defines_map.count(name) == 0)
+			if (ifdef_fail_level > 0 || !defines.find(name))
 				ifdef_fail_level++;
 			continue;
 		}
@@ -341,7 +766,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 		if (tok == "`ifndef") {
 			skip_spaces();
 			std::string name = next_token(true);
-			if (ifdef_fail_level > 0 || defines_map.count(name) != 0)
+			if (ifdef_fail_level > 0 || defines.find(name))
 				ifdef_fail_level++;
 			continue;
 		}
@@ -355,7 +780,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 		if (tok == "`include") {
 			skip_spaces();
 			std::string fn = next_token(true);
-			while (try_expand_macro(defines_with_args, defines_map, fn)) {
+			while (try_expand_macro(defines, fn)) {
 				fn = next_token();
 			}
 			while (1) {
@@ -433,74 +858,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 		}
 
 		if (tok == "`define") {
-			std::string name, value;
-			std::map<std::string, int> args;
-			skip_spaces();
-			name = next_token(true);
-			bool here_doc_mode = false;
-			int newline_count = 0;
-			int state = 0;
-			if (skip_spaces() != "")
-				state = 3;
-			while (!tok.empty()) {
-				tok = next_token();
-				if (tok == "\"\"\"") {
-					here_doc_mode = !here_doc_mode;
-					continue;
-				}
-				if (state == 0 && tok == "(") {
-					state = 1;
-					skip_spaces();
-				} else
-				if (state == 1) {
-					if (tok == ")")
-						state = 2;
-					else if (tok != ",") {
-						int arg_idx = args.size()+1;
-						args[tok] = arg_idx;
-					}
-					skip_spaces();
-				} else {
-					if (state != 2)
-						state = 3;
-					if (tok == "\n") {
-						if (here_doc_mode) {
-							value += " ";
-							newline_count++;
-						} else {
-							return_char('\n');
-							break;
-						}
-					} else
-					if (tok == "\\") {
-						char ch = next_char();
-						if (ch == '\n') {
-							value += " ";
-							newline_count++;
-						} else {
-							value += std::string("\\");
-							return_char(ch);
-						}
-					} else
-					if (args.count(tok) > 0)
-						value += stringf("`macro_%s_arg%d", name.c_str(), args.at(tok));
-					else
-						value += tok;
-				}
-			}
-			while (newline_count-- > 0)
-				return_char('\n');
-			if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) {
-				// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
-				defines_map[name] = value;
-				if (state == 2)
-					defines_with_args.insert(name);
-				else
-					defines_with_args.erase(name);
-				global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2);
-			} else {
-				log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str());
-			}
+			read_define(filename, defines, global_defines_cache);
 			continue;
 		}
 
@@ -509,8 +867,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 			skip_spaces();
 			name = next_token(true);
 			// printf("undef: >>%s<<\n", name.c_str());
-			defines_map.erase(name);
-			defines_with_args.erase(name);
+			defines.erase(name);
 			global_defines_cache.erase(name);
 			continue;
 		}
@@ -525,13 +882,12 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 		}
 
 		if (tok == "`resetall") {
-			defines_map.clear();
-			defines_with_args.clear();
+			defines.clear();
 			global_defines_cache.clear();
 			continue;
 		}
 
-		if (try_expand_macro(defines_with_args, defines_map, tok))
+		if (try_expand_macro(defines, tok))
 			continue;
 
 		output_code.push_back(tok);
diff --git a/frontends/verilog/preproc.h b/frontends/verilog/preproc.h
new file mode 100644
index 000000000..673d633c0
--- /dev/null
+++ b/frontends/verilog/preproc.h
@@ -0,0 +1,77 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  ---
+ *
+ *  The Verilog preprocessor.
+ *
+ */
+#ifndef VERILOG_PREPROC_H
+#define VERILOG_PREPROC_H
+
+#include "kernel/yosys.h"
+
+#include <iosfwd>
+#include <list>
+#include <memory>
+#include <string>
+
+YOSYS_NAMESPACE_BEGIN
+
+struct define_body_t;
+struct arg_map_t;
+
+struct define_map_t
+{
+	define_map_t();
+	~ define_map_t();
+
+	// Add a definition, overwriting any existing definition for name.
+	void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr);
+
+	// Merge in another map of definitions (which take precedence
+	// over anything currently defined).
+	void merge(const define_map_t &map);
+
+	// Find a definition by name. If no match, returns null.
+	const define_body_t *find(const std::string &name) const;
+
+	// Erase a definition by name (no effect if not defined).
+	void erase(const std::string &name);
+
+	// Clear any existing definitions
+	void clear();
+
+	// Print a list of definitions, using the log function
+	void log() const;
+
+	std::map<std::string, std::unique_ptr<define_body_t>> defines;
+};
+
+
+struct define_map_t;
+
+std::string
+frontend_verilog_preproc(std::istream                 &f,
+                         std::string                   filename,
+                         const define_map_t           &pre_defines,
+                         define_map_t                 &global_defines_cache,
+                         const std::list<std::string> &include_dirs);
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index f2c1c227f..a2334e654 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -27,6 +27,7 @@
  */
 
 #include "verilog_frontend.h"
+#include "preproc.h"
 #include "kernel/yosys.h"
 #include "libs/sha1/sha1.h"
 #include <stdarg.h>
@@ -253,7 +254,8 @@ struct VerilogFrontend : public Frontend {
 		bool flag_defer = false;
 		bool flag_noblackbox = false;
 		bool flag_nowb = false;
-		std::map<std::string, std::string> defines_map;
+		define_map_t defines_map;
+
 		std::list<std::string> include_dirs;
 		std::list<std::string> attributes;
 
@@ -369,7 +371,7 @@ struct VerilogFrontend : public Frontend {
 			}
 			if (arg == "-lib") {
 				lib_mode = true;
-				defines_map["BLACKBOX"] = string();
+				defines_map.add("BLACKBOX", "");
 				continue;
 			}
 			if (arg == "-nowb") {
@@ -421,7 +423,7 @@ struct VerilogFrontend : public Frontend {
 					value = name.substr(equal+1);
 					name = name.substr(0, equal);
 				}
-				defines_map[name] = value;
+				defines_map.add(name, value);
 				continue;
 			}
 			if (arg.compare(0, 2, "-D") == 0) {
@@ -430,7 +432,7 @@ struct VerilogFrontend : public Frontend {
 				std::string value;
 				if (equal != std::string::npos)
 					value = arg.substr(equal+1);
-				defines_map[name] = value;
+				defines_map.add(name, value);
 				continue;
 			}
 			if (arg == "-I" && argidx+1 < args.size()) {
@@ -460,7 +462,7 @@ struct VerilogFrontend : public Frontend {
 		std::string code_after_preproc;
 
 		if (!flag_nopp) {
-			code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, design->verilog_defines, include_dirs);
+			code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs);
 			if (flag_ppdump)
 				log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
 			lexin = new std::istringstream(code_after_preproc);
@@ -592,7 +594,7 @@ struct VerilogDefines : public Pass {
 					value = name.substr(equal+1);
 					name = name.substr(0, equal);
 				}
-				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				design->verilog_defines->add(name, value);
 				continue;
 			}
 			if (arg.compare(0, 2, "-D") == 0) {
@@ -601,27 +603,25 @@ struct VerilogDefines : public Pass {
 				std::string value;
 				if (equal != std::string::npos)
 					value = arg.substr(equal+1);
-				design->verilog_defines[name] = std::pair<std::string, bool>(value, false);
+				design->verilog_defines->add(name, value);
 				continue;
 			}
 			if (arg == "-U" && argidx+1 < args.size()) {
 				std::string name = args[++argidx];
-				design->verilog_defines.erase(name);
+				design->verilog_defines->erase(name);
 				continue;
 			}
 			if (arg.compare(0, 2, "-U") == 0) {
 				std::string name = arg.substr(2);
-				design->verilog_defines.erase(name);
+				design->verilog_defines->erase(name);
 				continue;
 			}
 			if (arg == "-reset") {
-				design->verilog_defines.clear();
+				design->verilog_defines->clear();
 				continue;
 			}
 			if (arg == "-list") {
-				for (auto &it : design->verilog_defines) {
-					log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str());
-				}
+				design->verilog_defines->log();
 				continue;
 			}
 			break;
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 73ea51e6c..636a4ceca 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -85,10 +85,6 @@ namespace VERILOG_FRONTEND
 	extern std::istream *lexin;
 }
 
-// the pre-processor
-std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map,
-		dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs);
-
 YOSYS_NAMESPACE_END
 
 // the usual bison/flex stuff
-- 
cgit v1.2.3


From f8c065ed1cb17057a8317ae5bd47500a6be60c5c Mon Sep 17 00:00:00 2001
From: Peter Crozier <peter@crozier.com>
Date: Fri, 27 Mar 2020 16:21:45 +0000
Subject: Inline productions to follow house style.

---
 frontends/verilog/verilog_parser.y | 62 ++++++++++++++++++--------------------
 1 file changed, 29 insertions(+), 33 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d31740c6a..be2872e59 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -374,7 +374,9 @@ hierarchical_type_id:
 	;
 
 module:
-	attr module_start TOK_ID {
+	attr TOK_MODULE {
+		enterTypeScope();
+	} TOK_ID {
 		do_not_require_port_stubs = false;
 		AstNode *mod = new AstNode(AST_MODULE);
 		ast_stack.back()->children.push_back(mod);
@@ -382,9 +384,9 @@ module:
 		current_ast_mod = mod;
 		port_stubs.clear();
 		port_counter = 0;
-		mod->str = *$3;
+		mod->str = *$4;
 		append_attr(mod, $1);
-		delete $3;
+		delete $4;
 	} module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
 		if (port_stubs.size() != 0)
 			frontend_verilog_yyerror("Missing details for module port `%s'.",
@@ -396,9 +398,6 @@ module:
 		exitTypeScope();
 	};
 
-module_start: TOK_MODULE	{ enterTypeScope(); }
-	;
-
 module_para_opt:
 	'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
 
@@ -500,12 +499,14 @@ module_arg:
 	};
 
 package:
-	attr package_start TOK_ID {
+	attr TOK_PACKAGE {
+		enterTypeScope();
+	} TOK_ID {
 		AstNode *mod = new AstNode(AST_PACKAGE);
 		ast_stack.back()->children.push_back(mod);
 		ast_stack.push_back(mod);
 		current_ast_mod = mod;
-		mod->str = *$3;
+		mod->str = *$4;
 		append_attr(mod, $1);
 	} ';' package_body TOK_ENDPACKAGE {
 		ast_stack.pop_back();
@@ -513,9 +514,6 @@ package:
 		exitTypeScope();
 	};
 
-package_start: TOK_PACKAGE	{ enterTypeScope(); }
-	;
-
 package_body:
 	package_body package_body_stmt
 	| // optional
@@ -526,7 +524,9 @@ package_body_stmt:
 	localparam_decl;
 
 interface:
-	interface_start TOK_ID {
+	TOK_INTERFACE {
+		enterTypeScope();
+	} TOK_ID {
 		do_not_require_port_stubs = false;
 		AstNode *intf = new AstNode(AST_INTERFACE);
 		ast_stack.back()->children.push_back(intf);
@@ -534,8 +534,8 @@ interface:
 		current_ast_mod = intf;
 		port_stubs.clear();
 		port_counter = 0;
-		intf->str = *$2;
-		delete $2;
+		intf->str = *$3;
+		delete $3;
 	} module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
 		if (port_stubs.size() != 0)
 			frontend_verilog_yyerror("Missing details for module port `%s'.",
@@ -546,9 +546,6 @@ interface:
 		exitTypeScope();
 	};
 
-interface_start: TOK_INTERFACE	{ enterTypeScope(); }
-	;
-
 interface_body:
 	interface_body interface_body_stmt |;
 
@@ -2234,21 +2231,21 @@ behavioral_stmt:
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
-	attr begin opt_label {
+	attr TOK_BEGIN {
+		enterTypeScope();
+	} opt_label {
 		AstNode *node = new AstNode(AST_BLOCK);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 		append_attr(node, $1);
-		if ($3 != NULL)
-			node->str = *$3;
+		if ($4 != NULL)
+			node->str = *$4;
 	} behavioral_stmt_list TOK_END opt_label {
 		exitTypeScope();
-		if ($3 != NULL && $7 != NULL && *$3 != *$7)
-			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
-		if ($3 != NULL)
-			delete $3;
-		if ($7 != NULL)
-			delete $7;
+		if ($4 != NULL && $8 != NULL && *$4 != *$8)
+			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
+		delete $4;
+		delete $8;
 		ast_stack.pop_back();
 	} |
 	attr TOK_FOR '(' {
@@ -2326,7 +2323,6 @@ behavioral_stmt:
 		ast_stack.pop_back();
 	};
 
-begin: TOK_BEGIN	{ enterTypeScope(); }
 	;
 
 unique_case_attr:
@@ -2544,17 +2540,17 @@ gen_stmt:
 		case_type_stack.pop_back();
 		ast_stack.pop_back();
 	} |
-	begin opt_label {
+	TOK_BEGIN {
+		enterTypeScope();
+	} opt_label {
 		AstNode *node = new AstNode(AST_GENBLOCK);
-		node->str = $2 ? *$2 : std::string();
+		node->str = $3 ? *$3 : std::string();
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} module_gen_body TOK_END opt_label {
 		exitTypeScope();
-		if ($2 != NULL)
-			delete $2;
-		if ($6 != NULL)
-			delete $6;
+		delete $3;
+		delete $7;
 		ast_stack.pop_back();
 	} |
 	TOK_MSG_TASKS {
-- 
cgit v1.2.3


From 92809bb1d3c225ab0c846a55979f6914dcfbd886 Mon Sep 17 00:00:00 2001
From: Diego H <diego@symbioticeda.com>
Date: Mon, 30 Mar 2020 17:18:13 -0600
Subject: Adding error message for when size (width) of number literal is zero

---
 frontends/verilog/const2ast.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 49281f7e7..25d257867 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -139,6 +139,10 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 		data.resize(len_in_bits, msb);
 	}
 
+	if (len_in_bits == 0)
+		log_error("Illegal integer constant size of zero in %s:%d (IEEE 1800-2012, 5.7).\n",
+				current_filename.c_str(), get_line_num());
+
 	if (len > len_in_bits)
 		log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n",
 			len_in_bits, len, current_filename.c_str(), get_line_num());
-- 
cgit v1.2.3


From c859bcf71bddbcceb36d276221a5eb490ed1cf4c Mon Sep 17 00:00:00 2001
From: Diego H <diego@symbioticeda.com>
Date: Tue, 31 Mar 2020 12:01:29 -0600
Subject: Replacing log_error for log_file_error due consistency

---
 frontends/verilog/const2ast.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 25d257867..230dfadbf 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -140,8 +140,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 	}
 
 	if (len_in_bits == 0)
-		log_error("Illegal integer constant size of zero in %s:%d (IEEE 1800-2012, 5.7).\n",
-				current_filename.c_str(), get_line_num());
+		log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
 
 	if (len > len_in_bits)
 		log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n",
-- 
cgit v1.2.3


From c3997c77a571ec4373aaeb1d263d2dacabf1c028 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 30 Mar 2020 21:14:51 +0100
Subject: verilog: Add location info for generate constructs

Signed-off-by: David Shah <dave@ds0.me>
---
 frontends/verilog/verilog_parser.y | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index be2872e59..3f28f828d 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2522,6 +2522,7 @@ gen_stmt:
 	} simple_behavioral_stmt ';' expr {
 		ast_stack.back()->children.push_back($6);
 	} ';' simple_behavioral_stmt ')' gen_stmt_block {
+		SET_AST_NODE_LOC(ast_stack.back(), @1, @11);
 		ast_stack.pop_back();
 	} |
 	TOK_IF '(' expr ')' {
@@ -2530,6 +2531,7 @@ gen_stmt:
 		ast_stack.push_back(node);
 		ast_stack.back()->children.push_back($3);
 	} gen_stmt_block opt_gen_else {
+		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
 		ast_stack.pop_back();
 	} |
 	case_type '(' expr ')' {
@@ -2538,6 +2540,7 @@ gen_stmt:
 		ast_stack.push_back(node);
 	} gen_case_body TOK_ENDCASE {
 		case_type_stack.pop_back();
+		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
 		ast_stack.pop_back();
 	} |
 	TOK_BEGIN {
@@ -2551,6 +2554,7 @@ gen_stmt:
 		exitTypeScope();
 		delete $3;
 		delete $7;
+		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
 		ast_stack.pop_back();
 	} |
 	TOK_MSG_TASKS {
@@ -2560,6 +2564,7 @@ gen_stmt:
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} opt_arg_list ';'{
+		SET_AST_NODE_LOC(ast_stack.back(), @1, @3);
 		ast_stack.pop_back();
 	};
 
@@ -2569,6 +2574,7 @@ gen_stmt_block:
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} gen_stmt_or_module_body_stmt {
+		SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
 		ast_stack.pop_back();
 	};
 
-- 
cgit v1.2.3


From fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Mar 2020 12:57:01 -0700
Subject: kernel: use more ID::*

---
 frontends/verilog/verilog_parser.y | 44 +++++++++++++++++++-------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3f28f828d..c02c82169 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -436,9 +436,9 @@ module_arg_opt_assignment:
 			wire->str = ast_stack.back()->children.back()->str;
 			if (ast_stack.back()->children.back()->is_input) {
 				AstNode *n = ast_stack.back()->children.back();
-				if (n->attributes.count("\\defaultvalue"))
-					delete n->attributes.at("\\defaultvalue");
-				n->attributes["\\defaultvalue"] = $2;
+				if (n->attributes.count(ID::defaultvalue))
+					delete n->attributes.at(ID::defaultvalue);
+				n->attributes[ID::defaultvalue] = $2;
 			} else
 			if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
 				ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
@@ -1511,24 +1511,24 @@ wire_name_and_opt_assign:
 		bool attr_anyseq = false;
 		bool attr_allconst = false;
 		bool attr_allseq = false;
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
-			ast_stack.back()->children.back()->attributes.erase("\\anyconst");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
+			ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
 			attr_anyconst = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
-			ast_stack.back()->children.back()->attributes.erase("\\anyseq");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
+			ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
 			attr_anyseq = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\allconst");
-			ast_stack.back()->children.back()->attributes.erase("\\allconst");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
+			ast_stack.back()->children.back()->attributes.erase(ID::allconst);
 			attr_allconst = true;
 		}
-		if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
-			delete ast_stack.back()->children.back()->attributes.at("\\allseq");
-			ast_stack.back()->children.back()->attributes.erase("\\allseq");
+		if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
+			delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
+			ast_stack.back()->children.back()->attributes.erase(ID::allseq);
 			attr_allseq = true;
 		}
 		if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
@@ -1552,9 +1552,9 @@ wire_name_and_opt_assign:
 		AstNode *wire = new AstNode(AST_IDENTIFIER);
 		wire->str = ast_stack.back()->children.back()->str;
 		if (astbuf1->is_input) {
-			if (astbuf1->attributes.count("\\defaultvalue"))
-				delete astbuf1->attributes.at("\\defaultvalue");
-			astbuf1->attributes["\\defaultvalue"] = $3;
+			if (astbuf1->attributes.count(ID::defaultvalue))
+				delete astbuf1->attributes.at(ID::defaultvalue);
+			astbuf1->attributes[ID::defaultvalue] = $3;
 		}
 		else if (astbuf1->is_reg || astbuf1->is_logic){
 			AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
@@ -2355,12 +2355,12 @@ case_type:
 
 opt_synopsys_attr:
 	opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
-		if (ast_stack.back()->attributes.count("\\full_case") == 0)
-			ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
+		if (ast_stack.back()->attributes.count(ID::full_case) == 0)
+			ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
 	} |
 	opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
-		if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
-			ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
+		if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
+			ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
 	} |
 	/* empty */;
 
-- 
cgit v1.2.3


From 956ecd48f71417b514c194a833a49238049e00b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Apr 2020 09:51:32 -0700
Subject: kernel: big fat patch to use more ID::*, otherwise ID(*)

---
 frontends/verilog/verilog_parser.y | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'frontends/verilog')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c02c82169..3bffa3986 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1544,7 +1544,7 @@ wire_name_and_opt_assign:
 				fcall->str = "\\$allconst";
 			if (attr_allseq)
 				fcall->str = "\\$allseq";
-			fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
+			fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
 		}
 	} |
@@ -1839,7 +1839,7 @@ cell_port:
 	attr TOK_WILDCARD_CONNECT {
 		if (!sv_mode)
 			frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
-		astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
+		astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
 	};
 
 always_comb_or_latch:
@@ -1863,7 +1863,7 @@ always_stmt:
 		AstNode *node = new AstNode(AST_ALWAYS);
 		append_attr(node, $1);
 		if ($2)
-			node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 	} always_cond {
@@ -1883,9 +1883,9 @@ always_stmt:
 		AstNode *node = new AstNode(AST_ALWAYS);
 		append_attr(node, $1);
 		if ($2)
-			node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
 		else
-			node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
+			node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 		AstNode *block = new AstNode(AST_BLOCK);
-- 
cgit v1.2.3