From 35008e6d40af212655b549f481f58f9c066be08a Mon Sep 17 00:00:00 2001 From: Anonymous Maarten Date: Wed, 17 Jun 2020 13:51:02 +0200 Subject: MSVC cannot omit operand in conditional --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b34a62248..15c231f3b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1481,7 +1481,7 @@ enum_name_decl: delete $1; SET_AST_NODE_LOC(node, @1, @1); delete node->children[0]; - node->children[0] = $2 ?: new AstNode(AST_NONE); + node->children[0] = $2 ? $2 : new AstNode(AST_NONE); astbuf2->children.push_back(node); } ; -- cgit v1.2.3 From 504f22061995d5b0ad6549e360ee1dded0e86116 Mon Sep 17 00:00:00 2001 From: Anonymous Maarten Date: Wed, 17 Jun 2020 13:52:45 +0200 Subject: MSVC does not understand __builtin_unreachable --- frontends/verilog/preproc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7905ea598..ea23139e2 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -591,7 +591,7 @@ read_define_args() default: // The only FSM states are 0-2 and we dealt with 2 at the start of the loop. - __builtin_unreachable(); + log_assert(false); } } -- cgit v1.2.3