From fb1c2be76ba065a3da04f279b11e1ed2e59c75c5 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 20 Mar 2023 12:50:14 +0100 Subject: verilog: Support void functions The difference between void functions and tasks is that always_comb's implicit sensitivity list behaves as if functions were inlined, but ignores signals read only in tasks. This only matters for event based simulation, and for synthesis we can treat a void function like a task. --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 958809319..249986668 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -276,6 +276,7 @@ TIME_SCALE_SUFFIX [munpf]?s "byte" { SV_KEYWORD(TOK_BYTE); } "shortint" { SV_KEYWORD(TOK_SHORTINT); } "longint" { SV_KEYWORD(TOK_LONGINT); } +"void" { SV_KEYWORD(TOK_VOID); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } -- cgit v1.2.3