From 777f2881d880c7690c33821a90c990a8cebd275d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 23 Nov 2017 08:48:17 +0100 Subject: Add Verilog "automatic" keyword (ignored in synthesis) --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 07d85bed8..d6d00c371 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -170,6 +170,7 @@ YOSYS_NAMESPACE_END "endgenerate" { return TOK_ENDGENERATE; } "while" { return TOK_WHILE; } "repeat" { return TOK_REPEAT; } +"automatic" { return TOK_AUTOMATIC; } "unique" { SV_KEYWORD(TOK_UNIQUE); } "unique0" { SV_KEYWORD(TOK_UNIQUE); } -- cgit v1.2.3