From 044ca9dde409e3c91542fe95513d6641110f8462 Mon Sep 17 00:00:00 2001
From: Rupert Swarbrick <rswarbrick@lowrisc.org>
Date: Tue, 17 Mar 2020 09:34:31 +0000
Subject: Add support for SystemVerilog-style `define to Verilog frontend

This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
---
 frontends/verilog/preproc.h | 77 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 frontends/verilog/preproc.h

(limited to 'frontends/verilog/preproc.h')

diff --git a/frontends/verilog/preproc.h b/frontends/verilog/preproc.h
new file mode 100644
index 000000000..673d633c0
--- /dev/null
+++ b/frontends/verilog/preproc.h
@@ -0,0 +1,77 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  ---
+ *
+ *  The Verilog preprocessor.
+ *
+ */
+#ifndef VERILOG_PREPROC_H
+#define VERILOG_PREPROC_H
+
+#include "kernel/yosys.h"
+
+#include <iosfwd>
+#include <list>
+#include <memory>
+#include <string>
+
+YOSYS_NAMESPACE_BEGIN
+
+struct define_body_t;
+struct arg_map_t;
+
+struct define_map_t
+{
+	define_map_t();
+	~ define_map_t();
+
+	// Add a definition, overwriting any existing definition for name.
+	void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr);
+
+	// Merge in another map of definitions (which take precedence
+	// over anything currently defined).
+	void merge(const define_map_t &map);
+
+	// Find a definition by name. If no match, returns null.
+	const define_body_t *find(const std::string &name) const;
+
+	// Erase a definition by name (no effect if not defined).
+	void erase(const std::string &name);
+
+	// Clear any existing definitions
+	void clear();
+
+	// Print a list of definitions, using the log function
+	void log() const;
+
+	std::map<std::string, std::unique_ptr<define_body_t>> defines;
+};
+
+
+struct define_map_t;
+
+std::string
+frontend_verilog_preproc(std::istream                 &f,
+                         std::string                   filename,
+                         const define_map_t           &pre_defines,
+                         define_map_t                 &global_defines_cache,
+                         const std::list<std::string> &include_dirs);
+
+YOSYS_NAMESPACE_END
+
+#endif
-- 
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