From c1f6ce8b33b1c06a4e38b621e27876d5715eb26d Mon Sep 17 00:00:00 2001 From: georgerennie Date: Tue, 1 Dec 2020 01:37:19 +0000 Subject: Fix SYNTHESIS always being defined in Verilog frontend --- frontends/verilog/preproc.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'frontends/verilog/preproc.cc') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index ea23139e2..752f7a7a8 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -321,7 +321,6 @@ struct define_body_t define_map_t::define_map_t() { add("YOSYS", "1"); - add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); } // We must define this destructor here (rather than relying on the default), because we need to -- cgit v1.2.3