From 607e957657fc56625de5c28ea9cd43c859017d96 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 17 Jun 2022 16:04:22 +0200 Subject: use new verific extensions library --- frontends/verific/verific.cc | 124 ++++++++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 54 deletions(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index bbf860c96..5e610c0f3 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -58,6 +58,9 @@ USING_YOSYS_NAMESPACE #ifdef YOSYSHQ_VERIFIC_EXTENSIONS #include "InitialAssertions.h" +#include "VerificBasePass.h" +#include "TemplateGenerator.h" +#include "FormalApplication.h" #endif #ifndef YOSYSHQ_VERIFIC_API_VERSION @@ -149,6 +152,8 @@ public: } }; +static YosysStreamCallBackHandler stream_cb; + // ================================================================== VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) : @@ -2345,6 +2350,64 @@ bool check_noverific_env() return false; return true; } + +void set_verific_global_flags() +{ + static bool g_set_verific_global_flags = true; + + if (g_set_verific_global_flags) + { + Message::SetConsoleOutput(0); + Message::RegisterCallBackMsg(msg_func); + + RuntimeFlags::SetVar("db_preserve_user_instances", 1); + RuntimeFlags::SetVar("db_preserve_user_nets", 1); + RuntimeFlags::SetVar("db_preserve_x", 1); + + RuntimeFlags::SetVar("db_allow_external_nets", 1); + RuntimeFlags::SetVar("db_infer_wide_operators", 1); + RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); + + RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); + RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); + +#ifdef VERIFIC_VHDL_SUPPORT + RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); + RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); + RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); + + RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); + RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); + + RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); + //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); + RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); +#endif + RuntimeFlags::SetVar("veri_preserve_assignments", 1); + RuntimeFlags::SetVar("veri_preserve_comments", 1); + RuntimeFlags::SetVar("veri_preserve_drivers", 1); + + // Workaround for VIPER #13851 + RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); + + // WARNING: instantiating unknown module 'XYZ' (VERI-1063) + Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + + // https://github.com/YosysHQ/yosys/issues/1055 + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + + RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); + +#ifndef DB_PRESERVE_INITIAL_VALUE +# warning Verific was built without DB_PRESERVE_INITIAL_VALUE. +#endif + + veri_file::RegisterCallBackVerificStream(&stream_cb); + + g_set_verific_global_flags = false; + } +} #endif struct VerificPass : public Pass { @@ -2549,8 +2612,6 @@ struct VerificPass : public Pass { #ifdef YOSYS_ENABLE_VERIFIC void execute(std::vector args, RTLIL::Design *design) override { - static bool set_verific_global_flags = true; - if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" @@ -2562,56 +2623,7 @@ struct VerificPass : public Pass { log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); - if (set_verific_global_flags) - { - Message::SetConsoleOutput(0); - Message::RegisterCallBackMsg(msg_func); - - RuntimeFlags::SetVar("db_preserve_user_instances", 1); - RuntimeFlags::SetVar("db_preserve_user_nets", 1); - RuntimeFlags::SetVar("db_preserve_x", 1); - - RuntimeFlags::SetVar("db_allow_external_nets", 1); - RuntimeFlags::SetVar("db_infer_wide_operators", 1); - RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); - - RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); - RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); - RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); - -#ifdef VERIFIC_VHDL_SUPPORT - RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); - RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); - RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); - - RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); - RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); - - RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); - //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); - RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); -#endif - RuntimeFlags::SetVar("veri_preserve_assignments", 1); - RuntimeFlags::SetVar("veri_preserve_comments", 1); - RuntimeFlags::SetVar("veri_preserve_drivers", 1); - - // Workaround for VIPER #13851 - RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); - - // WARNING: instantiating unknown module 'XYZ' (VERI-1063) - Message::SetMessageType("VERI-1063", VERIFIC_ERROR); - - // https://github.com/YosysHQ/yosys/issues/1055 - RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; - - RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); - -#ifndef DB_PRESERVE_INITIAL_VALUE -# warning Verific was built without DB_PRESERVE_INITIAL_VALUE. -#endif - - set_verific_global_flags = false; - } + set_verific_global_flags(); verific_verbose = 0; verific_sva_fsm_limit = 16; @@ -2630,8 +2642,6 @@ struct VerificPass : public Pass { int argidx = 1; std::string work = "work"; - YosysStreamCallBackHandler cb; - veri_file::RegisterCallBackVerificStream(&cb); if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || args[argidx] == "-set-info" || args[argidx] == "-set-ignore")) @@ -3208,6 +3218,12 @@ struct VerificPass : public Pass { #endif } VerificPass; + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS +VERIFIC_PASS(VerificTemplateGenerator, "template", "generate template") +VERIFIC_PASS(VerificFormalApplication, "formal_app", "running formal application") +#endif + struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } void help() override -- cgit v1.2.3 From 1fdbb42fdd51aa940e4331cdf5b4d1ff56738658 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 21 Jun 2022 18:06:16 +0200 Subject: Revert "use new verific extensions library" This reverts commit 607e957657fc56625de5c28ea9cd43c859017d96. --- frontends/verific/verific.cc | 124 +++++++++++++++++++------------------------ 1 file changed, 54 insertions(+), 70 deletions(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5e610c0f3..bbf860c96 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -58,9 +58,6 @@ USING_YOSYS_NAMESPACE #ifdef YOSYSHQ_VERIFIC_EXTENSIONS #include "InitialAssertions.h" -#include "VerificBasePass.h" -#include "TemplateGenerator.h" -#include "FormalApplication.h" #endif #ifndef YOSYSHQ_VERIFIC_API_VERSION @@ -152,8 +149,6 @@ public: } }; -static YosysStreamCallBackHandler stream_cb; - // ================================================================== VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) : @@ -2350,64 +2345,6 @@ bool check_noverific_env() return false; return true; } - -void set_verific_global_flags() -{ - static bool g_set_verific_global_flags = true; - - if (g_set_verific_global_flags) - { - Message::SetConsoleOutput(0); - Message::RegisterCallBackMsg(msg_func); - - RuntimeFlags::SetVar("db_preserve_user_instances", 1); - RuntimeFlags::SetVar("db_preserve_user_nets", 1); - RuntimeFlags::SetVar("db_preserve_x", 1); - - RuntimeFlags::SetVar("db_allow_external_nets", 1); - RuntimeFlags::SetVar("db_infer_wide_operators", 1); - RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); - - RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); - RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); - RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); - -#ifdef VERIFIC_VHDL_SUPPORT - RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); - RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); - RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); - - RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); - RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); - - RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); - //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); - RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); -#endif - RuntimeFlags::SetVar("veri_preserve_assignments", 1); - RuntimeFlags::SetVar("veri_preserve_comments", 1); - RuntimeFlags::SetVar("veri_preserve_drivers", 1); - - // Workaround for VIPER #13851 - RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); - - // WARNING: instantiating unknown module 'XYZ' (VERI-1063) - Message::SetMessageType("VERI-1063", VERIFIC_ERROR); - - // https://github.com/YosysHQ/yosys/issues/1055 - RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; - - RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); - -#ifndef DB_PRESERVE_INITIAL_VALUE -# warning Verific was built without DB_PRESERVE_INITIAL_VALUE. -#endif - - veri_file::RegisterCallBackVerificStream(&stream_cb); - - g_set_verific_global_flags = false; - } -} #endif struct VerificPass : public Pass { @@ -2612,6 +2549,8 @@ struct VerificPass : public Pass { #ifdef YOSYS_ENABLE_VERIFIC void execute(std::vector args, RTLIL::Design *design) override { + static bool set_verific_global_flags = true; + if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" @@ -2623,7 +2562,56 @@ struct VerificPass : public Pass { log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); - set_verific_global_flags(); + if (set_verific_global_flags) + { + Message::SetConsoleOutput(0); + Message::RegisterCallBackMsg(msg_func); + + RuntimeFlags::SetVar("db_preserve_user_instances", 1); + RuntimeFlags::SetVar("db_preserve_user_nets", 1); + RuntimeFlags::SetVar("db_preserve_x", 1); + + RuntimeFlags::SetVar("db_allow_external_nets", 1); + RuntimeFlags::SetVar("db_infer_wide_operators", 1); + RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); + + RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); + RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); + +#ifdef VERIFIC_VHDL_SUPPORT + RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); + RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); + RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); + + RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); + RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); + + RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); + //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); + RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); +#endif + RuntimeFlags::SetVar("veri_preserve_assignments", 1); + RuntimeFlags::SetVar("veri_preserve_comments", 1); + RuntimeFlags::SetVar("veri_preserve_drivers", 1); + + // Workaround for VIPER #13851 + RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); + + // WARNING: instantiating unknown module 'XYZ' (VERI-1063) + Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + + // https://github.com/YosysHQ/yosys/issues/1055 + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + + RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); + +#ifndef DB_PRESERVE_INITIAL_VALUE +# warning Verific was built without DB_PRESERVE_INITIAL_VALUE. +#endif + + set_verific_global_flags = false; + } verific_verbose = 0; verific_sva_fsm_limit = 16; @@ -2642,6 +2630,8 @@ struct VerificPass : public Pass { int argidx = 1; std::string work = "work"; + YosysStreamCallBackHandler cb; + veri_file::RegisterCallBackVerificStream(&cb); if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || args[argidx] == "-set-info" || args[argidx] == "-set-ignore")) @@ -3218,12 +3208,6 @@ struct VerificPass : public Pass { #endif } VerificPass; - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS -VERIFIC_PASS(VerificTemplateGenerator, "template", "generate template") -VERIFIC_PASS(VerificFormalApplication, "formal_app", "running formal application") -#endif - struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } void help() override -- cgit v1.2.3 From b80976b543fc9f19d8ac5e574b904f1f8c67cd49 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 30 Jun 2022 11:19:01 +0200 Subject: Update to new verific extensions inteface --- frontends/verific/verific.cc | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index bbf860c96..8ecf54472 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -57,7 +57,7 @@ USING_YOSYS_NAMESPACE #include "FileSystem.h" #ifdef YOSYSHQ_VERIFIC_EXTENSIONS -#include "InitialAssertions.h" +#include "VerificExtensions.h" #endif #ifndef YOSYSHQ_VERIFIC_API_VERSION @@ -2246,7 +2246,7 @@ void verific_import(Design *design, const std::map &par verific_params.Insert(i.first.c_str(), i.second.c_str()); #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - InitialAssertions::Rewrite("work", &verific_params); + VerificExtensions::ElaborateAndRewrite("work", &verific_params); #endif if (top.empty()) { @@ -2312,6 +2312,9 @@ void verific_import(Design *design, const std::map &par nl_todo.erase(it); } +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + VerificExtensions::Reset(); +#endif hier_tree::DeleteHierarchicalTree(); veri_file::Reset(); #ifdef VERIFIC_VHDL_SUPPORT @@ -2493,6 +2496,8 @@ struct VerificPass : public Pass { log("\n"); log(" -v, -vv\n"); log(" Verbose log messages. (-vv is even more verbose than -v.)\n"); + log(" -pp \n"); + log(" Pretty print design after elaboration to specified file.\n"); log("\n"); log("The following additional import options are useful for debugging the Verific\n"); log("bindings (for Yosys and/or Verific developers):\n"); @@ -2539,6 +2544,9 @@ struct VerificPass : public Pass { log("Get/set Verific runtime flags.\n"); log("\n"); log("\n"); +#if defined(YOSYS_ENABLE_VERIFIC) and defined(YOSYSHQ_VERIFIC_EXTENSIONS) + VerificExtensions::Help(); +#endif log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"); log("https://www.yosyshq.com/\n"); log("\n"); @@ -2922,6 +2930,7 @@ struct VerificPass : public Pass { bool mode_autocover = false, mode_fullinit = false; bool flatten = false, extnets = false; string dumpfile; + string ppfile; Map parameters(STRING_HASH); for (argidx++; argidx < GetSize(args); argidx++) { @@ -2990,6 +2999,10 @@ struct VerificPass : public Pass { dumpfile = args[++argidx]; continue; } + if (args[argidx] == "-pp" && argidx+1 < GetSize(args)) { + ppfile = args[++argidx]; + continue; + } break; } @@ -2999,8 +3012,11 @@ struct VerificPass : public Pass { std::set top_mod_names; #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - InitialAssertions::Rewrite(work, ¶meters); + VerificExtensions::ElaborateAndRewrite(work, ¶meters); #endif + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); + if (mode_all) { log("Running hier_tree::ElaborateAll().\n"); @@ -3113,6 +3129,9 @@ struct VerificPass : public Pass { nl_todo.erase(it); } +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + VerificExtensions::Reset(); +#endif hier_tree::DeleteHierarchicalTree(); veri_file::Reset(); #ifdef VERIFIC_VHDL_SUPPORT @@ -3187,6 +3206,13 @@ struct VerificPass : public Pass { } } } +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (VerificExtensions::Execute(args, argidx, work, + [this](const std::vector &args, size_t argidx, std::string msg) + { cmd_error(args, argidx, msg); } )) { + goto check_error; + } +#endif cmd_error(args, argidx, "Missing or unsupported mode parameter.\n"); -- cgit v1.2.3 From 59b96bb1f82b6cf83e004488267e5576dbcfad4b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 4 Jul 2022 11:09:06 +0200 Subject: Upadte documentation and changelog --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8ecf54472..fd6208e86 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2496,6 +2496,7 @@ struct VerificPass : public Pass { log("\n"); log(" -v, -vv\n"); log(" Verbose log messages. (-vv is even more verbose than -v.)\n"); + log("\n"); log(" -pp \n"); log(" Pretty print design after elaboration to specified file.\n"); log("\n"); -- cgit v1.2.3 From d19f9d0b66280d6d73275dbb030b91381ccda48b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= Date: Thu, 28 Jul 2022 12:32:19 +0200 Subject: Update README --- frontends/verific/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verific') diff --git a/frontends/verific/README b/frontends/verific/README index 952fb1e0c..921873af3 100644 --- a/frontends/verific/README +++ b/frontends/verific/README @@ -1,7 +1,7 @@ This directory contains Verific bindings for Yosys. -Use Tabby CAD Suite from YosysHQ if you need Yosys+Verifc. +Use Tabby CAD Suite from YosysHQ if you need Yosys+Verific. https://www.yosyshq.com/ Contact YosysHQ at contact@yosyshq.com for free evaluation -- cgit v1.2.3 From 52a4a89265b656a97bba441ac8f5c768bdd5c73e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 29 Jul 2022 17:10:31 +0200 Subject: Setting wire upto in verific import --- frontends/verific/verific.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fd6208e86..ab527a253 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1124,6 +1124,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size()); wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); + wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl); bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; @@ -1144,7 +1145,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->port_output = true; } net = portbus->ElementAtIndex(i)->GetNet(); - RTLIL::SigBit bit(wire, i - wire->start_offset); + int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset); + RTLIL::SigBit bit(wire, bitidx); if (net_map.count(net) == 0) net_map[net] = bit; else if (bit_input) @@ -1308,6 +1310,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex()); + wire->upto = netbus->IsUp(); MapIter mibus; FOREACH_NET_OF_NETBUS(netbus, mibus, net) { if (net) @@ -1322,7 +1325,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma { if (netbus->ElementAtIndex(i)) { - int bitidx = i - wire->start_offset; + int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset); net = netbus->ElementAtIndex(i); RTLIL::SigBit bit(wire, bitidx); -- cgit v1.2.3 From 2b1aeb44d98f4aafc73a66cdd02092571d725ee4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 8 Aug 2022 11:57:28 +0200 Subject: verific - make filepath handling compatible with verilog frontend --- frontends/verific/verific.cc | 44 +++++++++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 15 deletions(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ab527a253..e516a5ec7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2828,9 +2828,11 @@ struct VerificPass : public Pass { for (auto &ext : verific_libexts) veri_file::AddLibExt(ext.c_str()); - while (argidx < GetSize(args)) - file_names.Insert(args[argidx++].c_str()); - + while (argidx < GetSize(args)) { + std::string filename(args[argidx++]); + rewrite_filename(filename); + file_names.Insert(strdup(filename.c_str())); + } if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); @@ -2843,36 +2845,48 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87)) - log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87)) + log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93)) - log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93)) + log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K)) - log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K)) + log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008)) - log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008)) + log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } -- cgit v1.2.3 From 6c65ca4e50cc6712d9293b9630afdf67af89ef61 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 8 Aug 2022 16:13:33 +0200 Subject: Encode filename unprintable chars --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verific') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e516a5ec7..e0dbe1b32 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -183,7 +183,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) { std::string s = stringf("$verific$%s", obj->Name()); if (obj->Linefile()) - s += stringf("$%s:%d", Verific::LineFile::GetFileName(obj->Linefile()), Verific::LineFile::GetLineNo(obj->Linefile())); + s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())).c_str(), Verific::LineFile::GetLineNo(obj->Linefile())); s += stringf("$%d", autoidx++); return s; } -- cgit v1.2.3