From 5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c Mon Sep 17 00:00:00 2001 From: Vamsi K Vytla Date: Mon, 27 Apr 2020 09:44:24 -0700 Subject: Preserve 'signed'-ness of a verilog wire through RTLIL As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser --- frontends/ilang/ilang_parser.y | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/ilang') diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y index 8e21fb176..43b628e09 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/ilang/ilang_parser.y @@ -192,6 +192,9 @@ wire_options: wire_options TOK_UPTO { current_wire->upto = true; } | + wire_options TOK_SIGNED { + current_wire->is_signed = true; + } | wire_options TOK_OFFSET TOK_INT { current_wire->start_offset = $3; } | -- cgit v1.2.3