From cffec1f95f0ac4bad1deb24bf7f921bd93145a16 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 24 May 2022 14:32:14 +0200 Subject: verilog: fix signedness when removing unreachable cases --- frontends/ast/simplify.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/ast') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bd3e09c4b..4d7c4f522 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1531,6 +1531,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, detectSignWidth(width_hint, sign_hint); while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { + children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); std::vector new_children; new_children.push_back(children[0]); -- cgit v1.2.3