From a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 Nov 2016 12:42:43 +0100 Subject: Remember global declarations and defines accross read_verilog calls --- frontends/ast/ast.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'frontends/ast') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 92513a244..5b4a4af47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1016,14 +1016,12 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_icells = icells; flag_autowire = autowire; - std::vector global_decls; - log_assert(current_ast->type == AST_DESIGN); for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { if ((*it)->type == AST_MODULE) { - for (auto n : global_decls) + for (auto n : design->verilog_globals) (*it)->children.push_back(n->clone()); for (auto n : design->verilog_packages){ @@ -1054,7 +1052,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump else if ((*it)->type == AST_PACKAGE) design->verilog_packages.push_back((*it)->clone()); else - global_decls.push_back(*it); + design->verilog_globals.push_back((*it)->clone()); } } -- cgit v1.2.3