From 7ef0da32cdcddb50de8ba8acf0c6421fe5732c55 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 13 Jun 2014 11:29:23 +0200
Subject: Added Verilog lexer and parser support for real values

---
 frontends/ast/ast.cc | 5 +++++
 frontends/ast/ast.h  | 2 ++
 2 files changed, 7 insertions(+)

(limited to 'frontends/ast')

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 0780f7b59..1ce7efc84 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -77,6 +77,7 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_ARGUMENT)
 	X(AST_RANGE)
 	X(AST_CONSTANT)
+	X(AST_REALVALUE)
 	X(AST_CELLTYPE)
 	X(AST_IDENTIFIER)
 	X(AST_PREFIX)
@@ -460,6 +461,10 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
 			fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
 		break;
 
+	case AST_REALVALUE:
+		fprintf(f, "%e", realvalue);
+		break;
+
 	case AST_BLOCK:
 		if (children.size() == 1) {
 			children[0]->dumpVlog(f, indent);
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 802bf98ff..aeb56e352 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -55,6 +55,7 @@ namespace AST
 		AST_ARGUMENT,
 		AST_RANGE,
 		AST_CONSTANT,
+		AST_REALVALUE,
 		AST_CELLTYPE,
 		AST_IDENTIFIER,
 		AST_PREFIX,
@@ -153,6 +154,7 @@ namespace AST
 		bool is_input, is_output, is_reg, is_signed, is_string, range_valid;
 		int port_id, range_left, range_right;
 		uint32_t integer;
+		double realvalue;
 
 		// this is set by simplify and used during RTLIL generation
 		AstNode *id2ast;
-- 
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