From 436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 20 Oct 2018 12:45:51 +0200 Subject: Refactor code to avoid code duplication + added comments --- frontends/ast/genrtlil.cc | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) (limited to 'frontends/ast/genrtlil.cc') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 32b9af6e9..8a6849faa 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -870,27 +870,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (children.size() > 0) { for(size_t i=0; itype == AST_INTERFACEPORTTYPE) { - std::string name_type = children[i]->str; - size_t ndots = std::count(name_type.begin(), name_type.end(), '.'); - // Separate the interface instance name from any modports: - if (ndots == 0) { // Does not have modport - wire->attributes["\\interface_type"] = name_type; - } - else { - std::stringstream name_type_stream(name_type); - std::string segment; - std::vector seglist; - while(std::getline(name_type_stream, segment, '.')) { - seglist.push_back(segment); - } - if (ndots == 1) { // Has modport - wire->attributes["\\interface_type"] = seglist[0]; - wire->attributes["\\interface_modport"] = seglist[1]; - } - else { // Erroneous port type - log_error("More than two '.' in signal port type (%s)\n", name_type.c_str()); - } - } + std::pair res = AST::split_modport_from_type(children[i]->str); + wire->attributes["\\interface_type"] = res.first; + if (res.second != "") + wire->attributes["\\interface_modport"] = res.second; break; } } -- cgit v1.2.3 From 23b69ca32b2ef93fc4b3f724099bfecdee0af869 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 20 Oct 2018 23:48:53 +0200 Subject: Improve read_verilog range out of bounds warning Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'frontends/ast/genrtlil.cc') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 8a6849faa..59c309665 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1083,8 +1083,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", str.c_str()); else - log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n", - str.c_str(), chunk.width); + log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n", + children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { if (chunk.width + chunk.offset > source_width) { @@ -1097,11 +1097,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset += add_undef_bits_lsb; } if (add_undef_bits_lsb) - log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", - str.c_str(), add_undef_bits_lsb); + log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", + children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb); if (add_undef_bits_msb) - log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", - str.c_str(), add_undef_bits_msb); + log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", + children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb); } } } -- cgit v1.2.3