From 89c74ffd7189d4898feb476ff70376385d516eb2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Tue, 23 Feb 2021 16:48:29 +0100 Subject: verilog: Use proc memory writes in the frontend. --- frontends/ast/ast.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 1c9a6ee47..1447bf568 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -381,6 +381,8 @@ namespace AST_INTERNAL extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; extern bool current_always_clocked; + extern dict current_memwr_count; + extern dict> current_memwr_visible; struct LookaheadRewriter; struct ProcessGenerator; } -- cgit v1.2.3 From 3421979f00664443c77b0899d34438f979b4c51c Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Mon, 20 Apr 2020 14:41:55 +0100 Subject: Change the type of current_module to Module The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support. --- frontends/ast/ast.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 1447bf568..069479353 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -379,7 +379,7 @@ namespace AST_INTERNAL extern const dict *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; - extern AST::AstModule *current_module; + extern RTLIL::Module *current_module; extern bool current_always_clocked; extern dict current_memwr_count; extern dict> current_memwr_visible; -- cgit v1.2.3 From 0795b3ec076d8d2c0aa0d954b707271bd2f064bf Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 25 Mar 2021 14:06:05 -0400 Subject: verilog: fix case expression sign and width handling - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements --- frontends/ast/ast.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 069479353..9887d24ea 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -291,7 +291,7 @@ namespace AST // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); - RTLIL::SigSpec genWidthRTLIL(int width, const dict *new_subst_ptr = NULL); + RTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict *new_subst_ptr = NULL); // compare AST nodes bool operator==(const AstNode &other) const; -- cgit v1.2.3 From 72787f52fc31954e4b7dc3dc34d86705fc4e9dd1 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Tue, 8 Jun 2021 00:39:36 +0200 Subject: Fixing old e-mail addresses and deadnames s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf /gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+/N. Engelhardt /gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah /gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic /gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; --- frontends/ast/ast.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 9887d24ea..bb9f42a05 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -1,7 +1,7 @@ /* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2012 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above -- cgit v1.2.3 From 2e697f5655455fd8ce5fec40b94683a11ade24e8 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sat, 5 Jun 2021 16:21:09 -0400 Subject: verilog: check for module scope identifiers during width detection The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker(). --- frontends/ast/ast.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 9887d24ea..b6b15b738 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -326,6 +326,9 @@ namespace AST // helpers for locations std::string loc_string() const; + + // Helper for looking up identifiers which are prefixed with the current module name + std::string try_pop_module_prefix() const; }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code -- cgit v1.2.3 From a9c8ca21d583c58a38931389f90bbaae0caec0d6 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 22 Jun 2021 10:39:57 -0400 Subject: sv: fix two struct access bugs - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions) --- frontends/ast/ast.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 2bda8fa92..60c7de32d 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -370,6 +370,9 @@ namespace AST // Helper for setting the src attribute. void set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast); + + // struct helper exposed from simplify for genrtlil + AstNode *make_struct_member_range(AstNode *node, AstNode *member_node); } namespace AST_INTERNAL -- cgit v1.2.3 From 414154dd275b8cf9f0ffa071d12fc20fd6fee503 Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Thu, 21 May 2020 17:36:29 +0100 Subject: Add support for parsing the SystemVerilog 'bind' construct This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch). --- frontends/ast/ast.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 60c7de32d..57ce5605f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -160,7 +160,8 @@ namespace AST AST_TYPEDEF, AST_STRUCT, AST_UNION, - AST_STRUCT_ITEM + AST_STRUCT_ITEM, + AST_BIND }; struct AstSrcLocType { -- cgit v1.2.3 From 8bdc019730c665f678fc1f3bdd8ed96cf2f513d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Fri, 21 May 2021 02:27:06 +0200 Subject: verilog: Emit $meminit_v2 cell. Fixes #2447. --- frontends/ast/ast.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 57ce5605f..ba5a11b96 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -221,7 +221,7 @@ namespace AST AstSrcLocType location; // creating and deleting nodes - AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL); + AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr); AstNode *clone() const; void cloneInto(AstNode *other) const; void delete_children(); -- cgit v1.2.3 From ee2b5b7ed186414897a8a570a9e503c438803ad8 Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Mon, 20 Apr 2020 16:06:53 +0100 Subject: Generate an RTLIL representation of bind constructs This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class. --- frontends/ast/ast.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index ba5a11b96..63104bca4 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -284,6 +284,9 @@ namespace AST void dumpAst(FILE *f, std::string indent) const; void dumpVlog(FILE *f, std::string indent) const; + // Generate RTLIL for a bind construct + std::vector genBindings() const; + // used by genRTLIL() for detecting expression width and sign void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL); void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL); -- cgit v1.2.3 From bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Tue, 19 Oct 2021 18:43:30 -0600 Subject: Split out logic for reprocessing an AstModule This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version. --- frontends/ast/ast.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 63104bca4..66bbdd7b4 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -348,7 +348,7 @@ namespace AST RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool mayfail) override; RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail) override; std::string derive_common(RTLIL::Design *design, const dict ¶meters, AstNode **new_ast_out, bool quiet = false); - void reprocess_module(RTLIL::Design *design, const dict &local_interfaces) override; + void expand_interfaces(RTLIL::Design *design, const dict &local_interfaces) override; RTLIL::Module *clone() const override; void loadconfig() const; }; @@ -395,6 +395,18 @@ namespace AST_INTERNAL extern dict> current_memwr_visible; struct LookaheadRewriter; struct ProcessGenerator; + + // Create and add a new AstModule from new_ast, then use it to replace + // old_module in design, renaming old_module to move it out of the way. + // Return the new module. + // + // If original_ast is not null, it will be used as the AST node for the + // new module. Otherwise, new_ast will be used. + RTLIL::Module * + process_and_replace_module(RTLIL::Design *design, + RTLIL::Module *old_module, + AST::AstNode *new_ast, + AST::AstNode *original_ast = nullptr); } YOSYS_NAMESPACE_END -- cgit v1.2.3 From e833c6a418103feb30f0cc3e5c482da00ee9f820 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 19 Oct 2021 18:46:26 -0600 Subject: verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change --- frontends/ast/ast.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 66bbdd7b4..48ec9a063 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -262,6 +262,7 @@ namespace AST void mem2reg_remove(pool &mem2reg_set, vector &delnodes); void meminfo(int &mem_width, int &mem_size, int &addr_bits); bool detect_latch(const std::string &var); + const RTLIL::Module* lookup_cell_module(); // additional functionality for evaluating constant functions struct varinfo_t { @@ -313,8 +314,8 @@ namespace AST RTLIL::Const bitsAsConst(int width, bool is_signed); RTLIL::Const bitsAsConst(int width = -1); RTLIL::Const bitsAsUnsizedConst(int width); - RTLIL::Const asAttrConst(); - RTLIL::Const asParaConst(); + RTLIL::Const asAttrConst() const; + RTLIL::Const asParaConst() const; uint64_t asInt(bool is_signed); bool bits_only_01() const; bool asBool() const; @@ -349,6 +350,7 @@ namespace AST RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail) override; std::string derive_common(RTLIL::Design *design, const dict ¶meters, AstNode **new_ast_out, bool quiet = false); void expand_interfaces(RTLIL::Design *design, const dict &local_interfaces) override; + bool reprocess_if_necessary(RTLIL::Design *design) override; RTLIL::Module *clone() const override; void loadconfig() const; }; @@ -377,6 +379,14 @@ namespace AST // struct helper exposed from simplify for genrtlil AstNode *make_struct_member_range(AstNode *node, AstNode *member_node); + + // generate standard $paramod... derived module name; parameters should be + // in the order they are declared in the instantiated module + std::string derived_module_name(std::string stripped_name, const std::vector> ¶meters); + + // used to provide simplify() access to the current design for looking up + // modules, ports, wires, etc. + void set_simplify_design_context(const RTLIL::Design *design); } namespace AST_INTERNAL -- cgit v1.2.3