From f1a206ba03c5b6fba2672754d09cc649a60beeb8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:17:14 -0700
Subject: Revert "Remove sequential extension"

This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
---
 frontends/aiger/aigerparse.cc | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8ee487e5..7a467b91e 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -732,12 +732,19 @@ void AigerReader::parse_aiger_binary()
 void AigerReader::post_process()
 {
 	pool<IdString> seen_boxes;
-	unsigned ci_count = 0, co_count = 0;
+	pool<IdString> flops;
+	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
 		log_assert(box_module);
 
+		bool is_flop = false;
 		if (seen_boxes.insert(cell->type).second) {
+			if (box_module->attributes.count("\\abc_flop")) {
+				log_assert(flop_count < flopNum);
+				flops.insert(cell->type);
+				is_flop = true;
+			}
 			auto it = box_module->attributes.find("\\abc_carry");
 			if (it != box_module->attributes.end()) {
 				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
@@ -777,6 +784,8 @@ void AigerReader::post_process()
 				carry_out->port_id = ports.size();
 			}
 		}
+		else
+			is_flop = flops.count(cell->type);
 
 		// NB: Assume box_module->ports are sorted alphabetically
 		//     (as RTLIL::Module::fixup_ports() would do)
@@ -803,7 +812,25 @@ void AigerReader::post_process()
 				rhs.append(wire);
 			}
 
-			cell->setPort(port_name, rhs);
+			if (!is_flop || port_name != "\\$pastQ")
+				cell->setPort(port_name, rhs);
+		}
+
+		if (is_flop) {
+			RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
+			log_assert(d);
+			log_assert(d->port_output);
+			d->port_output = false;
+
+			RTLIL::Wire *q = inputs[piNum - flopNum + flop_count];
+			log_assert(q);
+			log_assert(q->port_input);
+			q->port_input = false;
+
+			flop_count++;
+			module->connect(q, d);
+			cell->set_bool_attribute("\\abc_flop");
+			continue;
 		}
 	}
 
@@ -907,6 +934,10 @@ void AigerReader::post_process()
 					}
 				}
 				log_debug(" -> %s\n", log_id(wire));
+				int init;
+				mf >> init;
+				if (init < 2)
+					wire->attributes["\\init"] = init;
 			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
-- 
cgit v1.2.3


From 79b6edb6397c530a7304eb4334f95324a4208aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 28 Sep 2019 23:48:17 -0700
Subject: Big rework; flop info now mostly in cells_sim.v

---
 frontends/aiger/aigerparse.cc | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7a467b91e..439311230 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -740,7 +740,7 @@ void AigerReader::post_process()
 
 		bool is_flop = false;
 		if (seen_boxes.insert(cell->type).second) {
-			if (box_module->attributes.count("\\abc_flop")) {
+			if (box_module->attributes.count("\\abc9_flop")) {
 				log_assert(flop_count < flopNum);
 				flops.insert(cell->type);
 				is_flop = true;
@@ -811,12 +811,18 @@ void AigerReader::post_process()
 				}
 				rhs.append(wire);
 			}
-
-			if (!is_flop || port_name != "\\$pastQ")
-				cell->setPort(port_name, rhs);
+			cell->setPort(port_name, rhs);
 		}
 
 		if (is_flop) {
+			Wire* port = box_module->wire("\\$currQ");
+			log_assert(port);
+			log_assert(co_count < outputs.size());
+			Wire *wire = outputs[co_count++];
+			log_assert(wire);
+			log_assert(wire->port_output);
+			wire->port_output = false;
+
 			RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
 			log_assert(d);
 			log_assert(d->port_output);
@@ -827,9 +833,10 @@ void AigerReader::post_process()
 			log_assert(q->port_input);
 			q->port_input = false;
 
+			auto ff = module->addCell(NEW_ID, "$__ABC_FF_");
+			ff->setPort("\\D", d);
+			ff->setPort("\\Q", q);
 			flop_count++;
-			module->connect(q, d);
-			cell->set_bool_attribute("\\abc_flop");
 			continue;
 		}
 	}
-- 
cgit v1.2.3


From f9bb3352944275acc6e82eaf53aebf3c964f68c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 16:36:42 -0700
Subject: Cleanup $currQ from aigerparse

---
 frontends/aiger/aigerparse.cc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d40f33447..594bf60ce 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -817,8 +817,6 @@ void AigerReader::post_process()
 		}
 
 		if (is_flop) {
-			Wire* port = box_module->wire("\\$currQ");
-			log_assert(port);
 			log_assert(co_count < outputs.size());
 			Wire *wire = outputs[co_count++];
 			log_assert(wire);
-- 
cgit v1.2.3


From 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 17:21:14 -0700
Subject: Fix merge issues

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 77a49c34f..4b66af3ad 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -833,7 +833,7 @@ void AigerReader::post_process()
 			log_assert(q->port_input);
 			q->port_input = false;
 
-			auto ff = module->addCell(NEW_ID, "$__ABC_FF_");
+			auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
 			ff->setPort("\\D", d);
 			ff->setPort("\\Q", q);
 			flop_count++;
-- 
cgit v1.2.3


From a5767474830756319ce0fff53b81573701ec0cd2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 15:40:46 -0800
Subject: Consistent log message, ignore 's' extension

---
 frontends/aiger/aigerparse.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 4b66af3ad..9374f1ab3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -432,7 +432,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 			else if (c == 'r') {
 				uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
 				flopNum = parse_xaiger_literal(f);
-				log_debug("flopNum: %u\n", flopNum);
+				log_debug("flopNum = %u\n", flopNum);
 				log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
 				f.ignore(flopNum * sizeof(uint32_t));
 			}
@@ -464,9 +464,10 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 					boxes.emplace_back(cell);
 				}
 			}
-			else if (c == 'a' || c == 'i' || c == 'o') {
+			else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
 				uint32_t dataSize = parse_xaiger_literal(f);
 				f.ignore(dataSize);
+				log_debug("ignoring '%c'\n", c);
 			}
 			else {
 				break;
-- 
cgit v1.2.3


From 69d8c1386a239372a2ab8910bf12d5d70701b7fa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 16:21:06 -0800
Subject: Do not connect undriven POs to 1'bx

---
 frontends/aiger/aigerparse.cc | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9374f1ab3..084107b35 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1005,15 +1005,10 @@ void AigerReader::post_process()
 			if (other_wire) {
 				other_wire->port_input = false;
 				other_wire->port_output = false;
-			}
-			if (wire->port_input) {
-				if (other_wire)
+				if (wire->port_input)
 					module->connect(other_wire, SigSpec(wire, i));
-			}
-			else {
-								  // Since we skip POs that are connected to Sx,
-								  // re-connect them here
-				module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
+				else
+					module->connect(SigSpec(wire, i), other_wire);
 			}
 		}
 	}
-- 
cgit v1.2.3


From ab667d3d47ceb07a41b571517b4effb0f4a4bf0b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 16:35:57 -0800
Subject: Call abc9 with "&write -n", and parse_xaiger() to cope

---
 frontends/aiger/aigerparse.cc | 177 ++++++++++++++++++++----------------------
 1 file changed, 85 insertions(+), 92 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 084107b35..8ff690464 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -376,105 +376,98 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 	if (n0)
 		module->connect(n0, State::S0);
 
+	int c = f.get();
+	if (c != 'c')
+		log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+	c = f.get();
+	log_assert(c == '\n');
+
 	// Parse footer (symbol table, comments, etc.)
 	std::string s;
-	bool comment_seen = false;
-	for (int c = f.peek(); c != EOF; c = f.peek()) {
-		if (comment_seen || c == 'c') {
-			if (!comment_seen) {
-				f.ignore(1);
-				c = f.peek();
-				comment_seen = true;
-			}
-			if (c == '\n')
-				break;
-			f.ignore(1);
-			// XAIGER extensions
-			if (c == 'm') {
-				uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				uint32_t lutNum = parse_xaiger_literal(f);
-				uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
-				ConstEvalAig ce(module);
-				for (unsigned i = 0; i < lutNum; ++i) {
-					uint32_t rootNodeID = parse_xaiger_literal(f);
-					uint32_t cutLeavesM = parse_xaiger_literal(f);
-					log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
-					RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
-					uint32_t nodeID;
-					RTLIL::SigSpec input_sig;
-					for (unsigned j = 0; j < cutLeavesM; ++j) {
-						nodeID = parse_xaiger_literal(f);
-						log_debug2("\t%u\n", nodeID);
-						RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
-						log_assert(wire);
-						input_sig.append(wire);
-					}
-					// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
-					ce.clear();
-					ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
-					RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
-					for (int j = 0; j < (1 << cutLeavesM); ++j) {
-						int gray = j ^ (j >> 1);
-						ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
-						RTLIL::SigBit o(output_sig);
-						bool success YS_ATTRIBUTE(unused) = ce.eval(o);
-						log_assert(success);
-						log_assert(o.wire == nullptr);
-						lut_mask[gray] = o.data;
-					}
-					RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
-					log_assert(output_cell);
-					module->remove(output_cell);
-					module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+	for (int c = f.get(); c != EOF; c = f.get()) {
+		// XAIGER extensions
+		if (c == 'm') {
+			uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			uint32_t lutNum = parse_xaiger_literal(f);
+			uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
+			ConstEvalAig ce(module);
+			for (unsigned i = 0; i < lutNum; ++i) {
+				uint32_t rootNodeID = parse_xaiger_literal(f);
+				uint32_t cutLeavesM = parse_xaiger_literal(f);
+				log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
+				RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
+				uint32_t nodeID;
+				RTLIL::SigSpec input_sig;
+				for (unsigned j = 0; j < cutLeavesM; ++j) {
+					nodeID = parse_xaiger_literal(f);
+					log_debug2("\t%u\n", nodeID);
+					RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
+					log_assert(wire);
+					input_sig.append(wire);
 				}
-			}
-			else if (c == 'r') {
-				uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				flopNum = parse_xaiger_literal(f);
-				log_debug("flopNum = %u\n", flopNum);
-				log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
-				f.ignore(flopNum * sizeof(uint32_t));
-			}
-			else if (c == 'n') {
-				parse_xaiger_literal(f);
-				f >> s;
-				log_debug("n: '%s'\n", s.c_str());
-			}
-			else if (c == 'h') {
-				f.ignore(sizeof(uint32_t));
-				uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				log_assert(version == 1);
-				uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				log_debug("ciNum = %u\n", ciNum);
-				uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				log_debug("coNum = %u\n", coNum);
-				piNum = parse_xaiger_literal(f);
-				log_debug("piNum = %u\n", piNum);
-				uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
-				log_debug("poNum = %u\n", poNum);
-				uint32_t boxNum = parse_xaiger_literal(f);
-				log_debug("boxNum = %u\n", boxNum);
-				for (unsigned i = 0; i < boxNum; i++) {
-					f.ignore(2*sizeof(uint32_t));
-					uint32_t boxUniqueId = parse_xaiger_literal(f);
-					log_assert(boxUniqueId > 0);
-					uint32_t oldBoxNum = parse_xaiger_literal(f);
-					RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
-					boxes.emplace_back(cell);
+				// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
+				ce.clear();
+				ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
+				RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
+				for (int j = 0; j < (1 << cutLeavesM); ++j) {
+					int gray = j ^ (j >> 1);
+					ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
+					RTLIL::SigBit o(output_sig);
+					bool success YS_ATTRIBUTE(unused) = ce.eval(o);
+					log_assert(success);
+					log_assert(o.wire == nullptr);
+					lut_mask[gray] = o.data;
 				}
+				RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
+				log_assert(output_cell);
+				module->remove(output_cell);
+				module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
 			}
-			else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
-				uint32_t dataSize = parse_xaiger_literal(f);
-				f.ignore(dataSize);
-				log_debug("ignoring '%c'\n", c);
-			}
-			else {
-				break;
+		}
+		else if (c == 'r') {
+			uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			flopNum = parse_xaiger_literal(f);
+			log_debug("flopNum = %u\n", flopNum);
+			log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+			f.ignore(flopNum * sizeof(uint32_t));
+		}
+		else if (c == 'n') {
+			parse_xaiger_literal(f);
+			f >> s;
+			log_debug("n: '%s'\n", s.c_str());
+		}
+		else if (c == 'h') {
+			f.ignore(sizeof(uint32_t));
+			uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			log_assert(version == 1);
+			uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			log_debug("ciNum = %u\n", ciNum);
+			uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			log_debug("coNum = %u\n", coNum);
+			piNum = parse_xaiger_literal(f);
+			log_debug("piNum = %u\n", piNum);
+			uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			log_debug("poNum = %u\n", poNum);
+			uint32_t boxNum = parse_xaiger_literal(f);
+			log_debug("boxNum = %u\n", boxNum);
+			for (unsigned i = 0; i < boxNum; i++) {
+				f.ignore(2*sizeof(uint32_t));
+				uint32_t boxUniqueId = parse_xaiger_literal(f);
+				log_assert(boxUniqueId > 0);
+				uint32_t oldBoxNum = parse_xaiger_literal(f);
+				RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
+				boxes.emplace_back(cell);
 			}
 		}
-		else
-			log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+		else if (c == 'a' || c == 'i' || c == 'o' || c == 's') {
+			uint32_t dataSize = parse_xaiger_literal(f);
+			f.ignore(dataSize);
+			log_debug("ignoring '%c'\n", c);
+		}
+		else {
+			break;
+		}
 	}
 
 	post_process();
-- 
cgit v1.2.3


From c0339bbbf16cee8121417f69305c7601122ff70c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 16:21:09 -0800
Subject: Name inputs/outputs of aiger 'i%d' and 'o%d'

---
 frontends/aiger/aigerparse.cc | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 8ff690464..65a9e30ae 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -610,11 +610,12 @@ void AigerReader::parse_aiger_binary()
 	std::string line;
 
 	// Parse inputs
+	int digits = ceil(log10(I));
 	for (unsigned i = 1; i <= I; ++i) {
 		log_debug2("%d is an input\n", i);
-		RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
+		RTLIL::Wire *wire = module->addWire(stringf("\\i%0*d", digits, i));
 		wire->port_input = true;
-		log_assert(!wire->port_output);
+		module->connect(createWireIfNotExists(module, i << 1), wire);
 		inputs.push_back(wire);
 	}
 
@@ -664,23 +665,15 @@ void AigerReader::parse_aiger_binary()
 	}
 
 	// Parse outputs
+	digits = ceil(log10(O));
 	for (unsigned i = 0; i < O; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
 		log_debug2("%d is an output\n", l1);
-		const unsigned variable = l1 >> 1;
-		const bool invert = l1 & 1;
-		RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
-		RTLIL::Wire *wire = module->wire(wire_name);
-		if (!wire)
-			wire = createWireIfNotExists(module, l1);
-		else if (wire->port_input || wire->port_output) {
-			RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-			module->connect(new_wire, wire);
-			wire = new_wire;
-		}
+		RTLIL::Wire *wire = module->addWire(stringf("\\o%0*d", digits, i));
 		wire->port_output = true;
+		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
 	}
 	std::getline(f, line); // Ignore up to start of next line
-- 
cgit v1.2.3


From 0875a078710a2d60ec3c55e9b5a87d97fd643f3b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 17 Dec 2019 15:43:21 -0800
Subject: read_xaiger to cope with optional '\n' after 'c'

---
 frontends/aiger/aigerparse.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 65a9e30ae..abc2f4144 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -379,8 +379,8 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 	int c = f.get();
 	if (c != 'c')
 		log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
-	c = f.get();
-	log_assert(c == '\n');
+	if (f.peek() == '\n')
+		f.get();
 
 	// Parse footer (symbol table, comments, etc.)
 	std::string s;
-- 
cgit v1.2.3


From 5f50e4f1121d139c3c9b842514c86cfc7712b32e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 17 Dec 2019 15:44:35 -0800
Subject: Cleanup xaiger, remove unnecessary complexity with inout

---
 frontends/aiger/aigerparse.cc | 27 ++++-----------------------
 1 file changed, 4 insertions(+), 23 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index abc2f4144..613723966 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -887,16 +887,7 @@ void AigerReader::post_process()
 					// simply connect the latter to the former
 					RTLIL::Wire* existing = module->wire(escaped_s);
 					if (!existing) {
-						if (escaped_s.ends_with("$inout.out")) {
-							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11));
-							log_assert(in_wire);
-							log_assert(in_wire->port_input && !in_wire->port_output);
-							in_wire->port_output = true;
-							module->connect(in_wire, wire);
-						}
-						else
-							module->rename(wire, escaped_s);
+						module->rename(wire, escaped_s);
 					}
 					else {
 						wire->port_output = false;
@@ -908,19 +899,9 @@ void AigerReader::post_process()
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
 					RTLIL::Wire* existing = module->wire(indexed_name);
 					if (!existing) {
-						if (escaped_s.ends_with("$inout.out")) {
-							wire->port_output = false;
-							RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index));
-							log_assert(in_wire);
-							log_assert(in_wire->port_input && !in_wire->port_output);
-							in_wire->port_output = true;
-							module->connect(in_wire, wire);
-						}
-						else {
-							module->rename(wire, indexed_name);
-							if (wideports)
-								wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-						}
+						module->rename(wire, indexed_name);
+						if (wideports)
+							wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
 					}
 					else {
 						module->connect(wire, existing);
-- 
cgit v1.2.3


From a6fdb9f5c1262e57d4aa292778c947773d9fe04d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 17 Dec 2019 15:50:01 -0800
Subject: aiger frontend to user shorter, $-prefixed, names

---
 frontends/aiger/aigerparse.cc | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 613723966..9cb05dfb3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -255,7 +255,7 @@ end_of_header:
 	else
 		log_abort();
 
-	RTLIL::Wire* n0 = module->wire("\\__0__");
+	RTLIL::Wire* n0 = module->wire("$0");
 	if (n0)
 		module->connect(n0, State::S0);
 
@@ -316,14 +316,14 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 {
 	const unsigned variable = literal >> 1;
 	const bool invert = literal & 1;
-	RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : ""));
+	RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : ""));
 	RTLIL::Wire *wire = module->wire(wire_name);
 	if (wire) return wire;
 	log_debug2("Creating %s\n", wire_name.c_str());
 	wire = module->addWire(wire_name);
 	wire->port_input = wire->port_output = false;
 	if (!invert) return wire;
-	RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable));
+	RTLIL::IdString wire_inv_name(stringf("$%d", variable));
 	RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
 	if (wire_inv) {
 		if (module->cell(wire_inv_name)) return wire;
@@ -335,7 +335,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	}
 
 	log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-	module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire);
+	module->addNotGate(stringf("$%d$not", variable), wire_inv, wire);
 
 	return wire;
 }
@@ -372,7 +372,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 	else
 		log_abort();
 
-	RTLIL::Wire* n0 = module->wire("\\__0__");
+	RTLIL::Wire* n0 = module->wire("$0");
 	if (n0)
 		module->connect(n0, State::S0);
 
@@ -396,13 +396,13 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 				uint32_t rootNodeID = parse_xaiger_literal(f);
 				uint32_t cutLeavesM = parse_xaiger_literal(f);
 				log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
-				RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
+				RTLIL::Wire *output_sig = module->wire(stringf("$%d", rootNodeID));
 				uint32_t nodeID;
 				RTLIL::SigSpec input_sig;
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
-					RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
+					RTLIL::Wire *wire = module->wire(stringf("$%d", nodeID));
 					log_assert(wire);
 					input_sig.append(wire);
 				}
@@ -419,10 +419,10 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 					log_assert(o.wire == nullptr);
 					lut_mask[gray] = o.data;
 				}
-				RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
+				RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID));
 				log_assert(output_cell);
 				module->remove(output_cell);
-				module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+				module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
 			}
 		}
 		else if (c == 'r') {
@@ -456,7 +456,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 				uint32_t boxUniqueId = parse_xaiger_literal(f);
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
-				RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
+				RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId));
 				boxes.emplace_back(cell);
 			}
 		}
@@ -544,7 +544,7 @@ void AigerReader::parse_aiger_ascii()
 		log_debug2("%d is an output\n", l1);
 		const unsigned variable = l1 >> 1;
 		const bool invert = l1 & 1;
-		RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
+		RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
 		RTLIL::Wire *wire = module->wire(wire_name);
 		if (!wire)
 			wire = createWireIfNotExists(module, l1);
@@ -613,7 +613,7 @@ void AigerReader::parse_aiger_binary()
 	int digits = ceil(log10(I));
 	for (unsigned i = 1; i <= I; ++i) {
 		log_debug2("%d is an input\n", i);
-		RTLIL::Wire *wire = module->addWire(stringf("\\i%0*d", digits, i));
+		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
 		wire->port_input = true;
 		module->connect(createWireIfNotExists(module, i << 1), wire);
 		inputs.push_back(wire);
@@ -671,7 +671,7 @@ void AigerReader::parse_aiger_binary()
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
 		log_debug2("%d is an output\n", l1);
-		RTLIL::Wire *wire = module->addWire(stringf("\\o%0*d", digits, i));
+		RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
 		wire->port_output = true;
 		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
@@ -915,7 +915,7 @@ void AigerReader::post_process()
 					wire->attributes["\\init"] = init;
 			}
 			else if (type == "box") {
-				RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
+				RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable));
 				if (cell) { // ABC could have optimised this box away
 					module->rename(cell, escaped_s);
 					for (const auto &i : cell->connections()) {
-- 
cgit v1.2.3


From e5ed8e8e2172c243bcca651eedd81053a5d7f575 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 16:50:22 -0800
Subject: parse_xaiger to reorder ports too

---
 frontends/aiger/aigerparse.cc | 67 +++++++++++++++++--------------------------
 1 file changed, 26 insertions(+), 41 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9cb05dfb3..3d00aee10 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -722,6 +722,7 @@ void AigerReader::post_process()
 {
 	pool<IdString> seen_boxes;
 	pool<IdString> flops;
+	dict<IdString, std::vector<IdString>> box_ports;
 	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
@@ -734,51 +735,35 @@ void AigerReader::post_process()
 				flops.insert(cell->type);
 				is_flop = true;
 			}
-			auto it = box_module->attributes.find("\\abc9_carry");
-			if (it != box_module->attributes.end()) {
-				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-				auto carry_in_out = it->second.decode_string();
-				auto pos = carry_in_out.find(',');
-				if (pos == std::string::npos)
-					log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
-				auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
-				carry_in = box_module->wire(carry_in_name);
-				if (!carry_in || !carry_in->port_input)
-					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
-
-				auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
-				carry_out = box_module->wire(carry_out_name);
-				if (!carry_out || !carry_out->port_output)
-					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
-
-				auto &ports = box_module->ports;
-				for (auto jt = ports.begin(); jt != ports.end(); ) {
-					RTLIL::Wire* w = box_module->wire(*jt);
-					log_assert(w);
-					if (w == carry_in || w == carry_out) {
-						jt = ports.erase(jt);
-						continue;
-					}
-					if (w->port_id > carry_in->port_id)
-						--w->port_id;
-					if (w->port_id > carry_out->port_id)
-						--w->port_id;
-					log_assert(w->port_input || w->port_output);
-					log_assert(ports[w->port_id-1] == w->name);
-					++jt;
-				}
-				ports.push_back(carry_in->name);
-				carry_in->port_id = ports.size();
-				ports.push_back(carry_out->name);
-				carry_out->port_id = ports.size();
-			}
 		}
 		else
 			is_flop = flops.count(cell->type);
 
-		// NB: Assume box_module->ports are sorted alphabetically
-		//     (as RTLIL::Module::fixup_ports() would do)
-		for (auto port_name : box_module->ports) {
+		auto r = box_ports.insert(cell->type);
+		if (r.second) {
+			// Make carry in the last PI, and carry out the last PO
+			//   since ABC requires it this way
+			IdString carry_in, carry_out;
+			for (const auto &port_name : box_module->ports) {
+				auto w = box_module->wire(port_name);
+				log_assert(w);
+				if (w->get_bool_attribute("\\abc9_carry")) {
+					if (w->port_input)
+						carry_in = port_name;
+					if (w->port_output)
+						carry_out = port_name;
+				}
+				else
+					r.first->second.push_back(port_name);
+			}
+			if (carry_in != IdString()) {
+				log_assert(carry_out != IdString());
+				r.first->second.push_back(carry_in);
+				r.first->second.push_back(carry_out);
+			}
+		}
+
+		for (auto port_name : box_ports.at(cell->type)) {
 			RTLIL::Wire* port = box_module->wire(port_name);
 			log_assert(port);
 			RTLIL::SigSpec rhs;
-- 
cgit v1.2.3


From 96db05aaefd970c819ba1f75b7246c5958527b8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 17:06:03 -0800
Subject: parse_xaiger to not take box_lookup

---
 frontends/aiger/aigerparse.cc | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 3d00aee10..f030933ec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -340,7 +340,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	return wire;
 }
 
-void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
+void AigerReader::parse_xaiger()
 {
 	std::string header;
 	f >> header;
@@ -382,6 +382,21 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 	if (f.peek() == '\n')
 		f.get();
 
+	dict<int,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		auto it = m->attributes.find(ID(abc9_box_id));
+		if (it == m->attributes.end())
+			continue;
+		if (m->name.begins_with("$paramod"))
+			continue;
+		auto id = it->second.as_int();
+		auto r = box_lookup.insert(std::make_pair(id, m->name));
+		if (!r.second)
+			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+					log_id(m), id, log_id(r.first->second));
+		log_assert(r.second);
+	}
+
 	// Parse footer (symbol table, comments, etc.)
 	std::string s;
 	for (int c = f.get(); c != EOF; c = f.get()) {
@@ -456,7 +471,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 				uint32_t boxUniqueId = parse_xaiger_literal(f);
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
-				RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId));
+				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
 				boxes.emplace_back(cell);
 			}
 		}
@@ -720,25 +735,12 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-	pool<IdString> seen_boxes;
-	pool<IdString> flops;
 	dict<IdString, std::vector<IdString>> box_ports;
 	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
 		log_assert(box_module);
 
-		bool is_flop = false;
-		if (seen_boxes.insert(cell->type).second) {
-			if (box_module->attributes.count("\\abc9_flop")) {
-				log_assert(flop_count < flopNum);
-				flops.insert(cell->type);
-				is_flop = true;
-			}
-		}
-		else
-			is_flop = flops.count(cell->type);
-
 		auto r = box_ports.insert(cell->type);
 		if (r.second) {
 			// Make carry in the last PI, and carry out the last PO
@@ -788,7 +790,7 @@ void AigerReader::post_process()
 			cell->setPort(port_name, rhs);
 		}
 
-		if (is_flop) {
+		if (box_module->attributes.count("\\abc9_flop")) {
 			log_assert(co_count < outputs.size());
 			Wire *wire = outputs[co_count++];
 			log_assert(wire);
@@ -900,7 +902,7 @@ void AigerReader::post_process()
 					wire->attributes["\\init"] = init;
 			}
 			else if (type == "box") {
-				RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable));
+				RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
 				if (cell) { // ABC could have optimised this box away
 					module->rename(cell, escaped_s);
 					for (const auto &i : cell->connections()) {
-- 
cgit v1.2.3


From 83616e7866138a91d0b4f60b02e32877c1a34ac1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 6 Jan 2020 12:43:29 -0800
Subject: read_aiger: add -xaiger option

---
 frontends/aiger/aigerparse.cc | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f030933ec..d6efdaafe 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1000,18 +1000,21 @@ struct AigerFrontend : public Frontend {
 		log("Load module from an AIGER file into the current design.\n");
 		log("\n");
 		log("    -module_name <module_name>\n");
-		log("        Name of module to be created (default: <filename>)\n");
+		log("        name of module to be created (default: <filename>)\n");
 		log("\n");
 		log("    -clk_name <wire_name>\n");
-		log("        If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
-		log("        clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
+		log("        if specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
+		log("        clocked by wire of this name. otherwise, $_FF_ cells will be used\n");
 		log("\n");
 		log("    -map <filename>\n");
 		log("        read file with port and latch symbols\n");
 		log("\n");
 		log("    -wideports\n");
-		log("        Merge ports that match the pattern 'name[int]' into a single\n");
-		log("        multi-bit port 'name'.\n");
+		log("        merge ports that match the pattern 'name[int]' into a single\n");
+		log("        multi-bit port 'name'\n");
+		log("\n");
+		log("    -xaiger\n");
+		log("        read XAIGER extensions\n");
 		log("\n");
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -1021,7 +1024,7 @@ struct AigerFrontend : public Frontend {
 		RTLIL::IdString clk_name = "\\clk";
 		RTLIL::IdString module_name;
 		std::string map_filename;
-		bool wideports = false;
+		bool wideports = false, xaiger = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
@@ -1042,6 +1045,10 @@ struct AigerFrontend : public Frontend {
 				wideports = true;
 				continue;
 			}
+			if (arg == "-xaiger") {
+				xaiger = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx, true);
@@ -1061,7 +1068,10 @@ struct AigerFrontend : public Frontend {
 		}
 
 		AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
-		reader.parse_aiger();
+		if (xaiger)
+			reader.parse_xaiger();
+		else
+			reader.parse_aiger();
 	}
 } AigerFrontend;
 
-- 
cgit v1.2.3


From b57f692a9e5b2fe9b9f63f329f29d933347a2c40 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 09:32:34 -0800
Subject: read_aiger: consistency between ascii and binary

---
 frontends/aiger/aigerparse.cc | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d6efdaafe..f937ae1f0 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -496,13 +496,14 @@ void AigerReader::parse_aiger_ascii()
 	unsigned l1, l2, l3;
 
 	// Parse inputs
+	int digits = ceil(log10(I));
 	for (unsigned i = 1; i <= I; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an input!\n", line_count);
 		log_debug2("%d is an input\n", l1);
-		log_assert(!(l1 & 1)); // Inputs can't be inverted
-		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1));
 		wire->port_input = true;
+		module->connect(createWireIfNotExists(module, l1 << 1), wire);
 		inputs.push_back(wire);
 	}
 
@@ -552,25 +553,18 @@ void AigerReader::parse_aiger_ascii()
 	}
 
 	// Parse outputs
+	digits = ceil(log10(O));
 	for (unsigned i = 0; i < O; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
 		log_debug2("%d is an output\n", l1);
-		const unsigned variable = l1 >> 1;
-		const bool invert = l1 & 1;
-		RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
-		RTLIL::Wire *wire = module->wire(wire_name);
-		if (!wire)
-			wire = createWireIfNotExists(module, l1);
-		else if (wire->port_input || wire->port_output) {
-			RTLIL::Wire *new_wire = module->addWire(NEW_ID);
-			module->connect(new_wire, wire);
-			wire = new_wire;
-		}
+		RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i));
 		wire->port_output = true;
+		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
 	}
+	std::getline(f, line); // Ignore up to start of next line
 
 	// Parse bad properties
 	for (unsigned i = 0; i < B; ++i, ++line_count) {
-- 
cgit v1.2.3


From 61a2a60595f60acd4d46344e4c974153bbdfe8e3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 09:48:11 -0800
Subject: read_aiger: do not process box connections, work standalone

---
 frontends/aiger/aigerparse.cc | 161 ++++++++++++------------------------------
 1 file changed, 46 insertions(+), 115 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f937ae1f0..355429646 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -382,21 +382,6 @@ void AigerReader::parse_xaiger()
 	if (f.peek() == '\n')
 		f.get();
 
-	dict<int,IdString> box_lookup;
-	for (auto m : design->modules()) {
-		auto it = m->attributes.find(ID(abc9_box_id));
-		if (it == m->attributes.end())
-			continue;
-		if (m->name.begins_with("$paramod"))
-			continue;
-		auto id = it->second.as_int();
-		auto r = box_lookup.insert(std::make_pair(id, m->name));
-		if (!r.second)
-			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-					log_id(m), id, log_id(r.first->second));
-		log_assert(r.second);
-	}
-
 	// Parse footer (symbol table, comments, etc.)
 	std::string s;
 	for (int c = f.get(); c != EOF; c = f.get()) {
@@ -467,11 +452,14 @@ void AigerReader::parse_xaiger()
 			uint32_t boxNum = parse_xaiger_literal(f);
 			log_debug("boxNum = %u\n", boxNum);
 			for (unsigned i = 0; i < boxNum; i++) {
-				f.ignore(2*sizeof(uint32_t));
+				uint32_t boxInputs = parse_xaiger_literal(f);
+				uint32_t boxOutputs = parse_xaiger_literal(f);
 				uint32_t boxUniqueId = parse_xaiger_literal(f);
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
-				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
+				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
+				cell->setPort("\\i", SigSpec(State::S0, boxInputs));
+				cell->setPort("\\o", SigSpec(State::S0, boxOutputs));
 				boxes.emplace_back(cell);
 			}
 		}
@@ -501,7 +489,8 @@ void AigerReader::parse_aiger_ascii()
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an input!\n", line_count);
 		log_debug2("%d is an input\n", l1);
-		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1));
+		log_assert(!(l1 & 1)); // Inputs can't be inverted
+		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
 		wire->port_input = true;
 		module->connect(createWireIfNotExists(module, l1 << 1), wire);
 		inputs.push_back(wire);
@@ -576,6 +565,8 @@ void AigerReader::parse_aiger_ascii()
 		wire->port_output = true;
 		bad_properties.push_back(wire);
 	}
+	if (B > 0)
+		std::getline(f, line); // Ignore up to start of next line
 
 	// TODO: Parse invariant constraints
 	for (unsigned i = 0; i < C; ++i, ++line_count)
@@ -729,84 +720,46 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-	dict<IdString, std::vector<IdString>> box_ports;
-	unsigned ci_count = 0, co_count = 0, flop_count = 0;
+	unsigned ci_count = 0, co_count = 0;
 	for (auto cell : boxes) {
-		RTLIL::Module* box_module = design->module(cell->type);
-		log_assert(box_module);
-
-		auto r = box_ports.insert(cell->type);
-		if (r.second) {
-			// Make carry in the last PI, and carry out the last PO
-			//   since ABC requires it this way
-			IdString carry_in, carry_out;
-			for (const auto &port_name : box_module->ports) {
-				auto w = box_module->wire(port_name);
-				log_assert(w);
-				if (w->get_bool_attribute("\\abc9_carry")) {
-					if (w->port_input)
-						carry_in = port_name;
-					if (w->port_output)
-						carry_out = port_name;
-				}
-				else
-					r.first->second.push_back(port_name);
-			}
-			if (carry_in != IdString()) {
-				log_assert(carry_out != IdString());
-				r.first->second.push_back(carry_in);
-				r.first->second.push_back(carry_out);
-			}
+		for (auto &bit : cell->connections_.at("\\i")) {
+			log_assert(bit == State::S0);
+			log_assert(co_count < outputs.size());
+			bit = outputs[co_count++];
+			log_assert(bit.wire && GetSize(bit.wire) == 1);
+			log_assert(bit.wire->port_output);
+			bit.wire->port_output = false;
 		}
-
-		for (auto port_name : box_ports.at(cell->type)) {
-			RTLIL::Wire* port = box_module->wire(port_name);
-			log_assert(port);
-			RTLIL::SigSpec rhs;
-			for (int i = 0; i < GetSize(port); i++) {
-				RTLIL::Wire* wire = nullptr;
-				if (port->port_input) {
-					log_assert(co_count < outputs.size());
-					wire = outputs[co_count++];
-					log_assert(wire);
-					log_assert(wire->port_output);
-					wire->port_output = false;
-				}
-				if (port->port_output) {
-					log_assert((piNum + ci_count) < inputs.size());
-					wire = inputs[piNum + ci_count++];
-					log_assert(wire);
-					log_assert(wire->port_input);
-					wire->port_input = false;
-				}
-				rhs.append(wire);
-			}
-			cell->setPort(port_name, rhs);
+		for (auto &bit : cell->connections_.at("\\o")) {
+			log_assert(bit == State::S0);
+			log_assert((piNum + ci_count) < inputs.size());
+			bit = inputs[piNum + ci_count++];
+			log_assert(bit.wire && GetSize(bit.wire) == 1);
+			log_assert(bit.wire->port_input);
+			bit.wire->port_input = false;
 		}
+	}
 
-		if (box_module->attributes.count("\\abc9_flop")) {
-			log_assert(co_count < outputs.size());
-			Wire *wire = outputs[co_count++];
-			log_assert(wire);
-			log_assert(wire->port_output);
-			wire->port_output = false;
-
-			RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count];
-			log_assert(d);
-			log_assert(d->port_output);
-			d->port_output = false;
-
-			RTLIL::Wire *q = inputs[piNum - flopNum + flop_count];
-			log_assert(q);
-			log_assert(q->port_input);
-			q->port_input = false;
-
-			auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
-			ff->setPort("\\D", d);
-			ff->setPort("\\Q", q);
-			flop_count++;
-			continue;
-		}
+	for (uint32_t i = 0; i < flopNum; i++) {
+		log_assert(co_count < outputs.size());
+		Wire *wire = outputs[co_count++];
+		log_assert(wire);
+		log_assert(wire->port_output);
+		wire->port_output = false;
+
+		RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
+		log_assert(d);
+		log_assert(d->port_output);
+		d->port_output = false;
+
+		RTLIL::Wire *q = inputs[piNum - flopNum + i];
+		log_assert(q);
+		log_assert(q->port_input);
+		q->port_input = false;
+
+		auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
+		ff->setPort("\\D", d);
+		ff->setPort("\\Q", q);
 	}
 
 	dict<RTLIL::IdString, int> wideports_cache;
@@ -856,10 +809,6 @@ void AigerReader::post_process()
 				RTLIL::Wire* wire = outputs[variable + co_count];
 				log_assert(wire);
 				log_assert(wire->port_output);
-				if (escaped_s == "$__dummy__") {
-					wire->port_output = false;
-					continue;
-				}
 				log_debug("Renaming output %s", log_id(wire));
 
 				if (index == 0) {
@@ -897,26 +846,8 @@ void AigerReader::post_process()
 			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
-				if (cell) { // ABC could have optimised this box away
+				if (cell) // ABC could have optimised this box away
 					module->rename(cell, escaped_s);
-					for (const auto &i : cell->connections()) {
-						RTLIL::IdString port_name = i.first;
-						RTLIL::SigSpec rhs = i.second;
-						int index = 0;
-						for (auto bit : rhs.bits()) {
-							RTLIL::Wire* wire = bit.wire;
-							RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
-							if (index == 0)
-								module->rename(wire, escaped_s);
-							else if (index > 0) {
-								module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
-								if (wideports)
-									wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
-							}
-							index++;
-						}
-					}
-				}
 			}
 			else
 				log_error("Symbol type '%s' not recognised.\n", type.c_str());
-- 
cgit v1.2.3


From 738af17a26587f6f9438bfa2452e65a5911e58e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 11:21:45 -0800
Subject: read_aiger: default -clk_name to be empty

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f030933ec..d7367479b 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1018,7 +1018,7 @@ struct AigerFrontend : public Frontend {
 	{
 		log_header(design, "Executing AIGER frontend.\n");
 
-		RTLIL::IdString clk_name = "\\clk";
+		RTLIL::IdString clk_name;
 		RTLIL::IdString module_name;
 		std::string map_filename;
 		bool wideports = false;
-- 
cgit v1.2.3


From baba33fbd391d31187695a8d0d9937249a472b2e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 11:22:48 -0800
Subject: read_aiger: cope with latches and POs with same name

---
 frontends/aiger/aigerparse.cc | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d7367479b..04530e562 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -271,14 +271,23 @@ end_of_header:
 			if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
 				log_error("Line %u has invalid symbol position!\n", line_count);
 
+			RTLIL::IdString escaped_s = stringf("\\%s", s.c_str());
 			RTLIL::Wire* wire;
 			if (c == 'i') wire = inputs[l1];
 			else if (c == 'l') wire = latches[l1];
-			else if (c == 'o') wire = outputs[l1];
+			else if (c == 'o') {
+				wire = module->wire(escaped_s);
+				if (wire) {
+					// Could have been renamed by a latch
+					module->swap_names(wire, outputs[l1]);
+					goto next;
+				}
+				wire = outputs[l1];
+			}
 			else if (c == 'b') wire = bad_properties[l1];
 			else log_abort();
 
-			module->rename(wire, stringf("\\%s", s.c_str()));
+			module->rename(wire, escaped_s);
 		}
 		else if (c == 'j' || c == 'f') {
 			// TODO
@@ -293,6 +302,7 @@ end_of_header:
 		}
 		else
 			log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+next:
 		std::getline(f, line); // Ignore up to start of next line
 	}
 
-- 
cgit v1.2.3


From b94cf0c1266f6f3daea809323f0bba0dc5d69e1a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 11:43:28 -0800
Subject: read_aiger: connect identical signals together

---
 frontends/aiger/aigerparse.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 04530e562..f7b9146ce 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -280,6 +280,7 @@ end_of_header:
 				if (wire) {
 					// Could have been renamed by a latch
 					module->swap_names(wire, outputs[l1]);
+					module->connect(outputs[l1], wire);
 					goto next;
 				}
 				wire = outputs[l1];
-- 
cgit v1.2.3


From 8f5388ea5b88d4e848b1110fed2abf7544440185 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 11:59:57 -0800
Subject: read_aiger fixes

---
 frontends/aiger/aigerparse.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 355429646..b18049df1 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -490,9 +490,9 @@ void AigerReader::parse_aiger_ascii()
 			log_error("Line %u cannot be interpreted as an input!\n", line_count);
 		log_debug2("%d is an input\n", l1);
 		log_assert(!(l1 & 1)); // Inputs can't be inverted
-		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
+		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1 >> 1));
 		wire->port_input = true;
-		module->connect(createWireIfNotExists(module, l1 << 1), wire);
+		module->connect(createWireIfNotExists(module, l1), wire);
 		inputs.push_back(wire);
 	}
 
@@ -553,7 +553,7 @@ void AigerReader::parse_aiger_ascii()
 		module->connect(wire, createWireIfNotExists(module, l1));
 		outputs.push_back(wire);
 	}
-	std::getline(f, line); // Ignore up to start of next line
+	//std::getline(f, line); // Ignore up to start of next line
 
 	// Parse bad properties
 	for (unsigned i = 0; i < B; ++i, ++line_count) {
@@ -565,8 +565,8 @@ void AigerReader::parse_aiger_ascii()
 		wire->port_output = true;
 		bad_properties.push_back(wire);
 	}
-	if (B > 0)
-		std::getline(f, line); // Ignore up to start of next line
+	//if (B > 0)
+	//	std::getline(f, line); // Ignore up to start of next line
 
 	// TODO: Parse invariant constraints
 	for (unsigned i = 0; i < C; ++i, ++line_count)
-- 
cgit v1.2.3


From 2ac36031d4da8d2e99d89f16cb69871c9e3c59aa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 13:30:31 -0800
Subject: read_aiger: consistency between ascii and binary; also name latches

---
 frontends/aiger/aigerparse.cc | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f7b9146ce..8a114b18c 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -507,13 +507,15 @@ void AigerReader::parse_aiger_ascii()
 	unsigned l1, l2, l3;
 
 	// Parse inputs
+	int digits = ceil(log10(I));
 	for (unsigned i = 1; i <= I; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an input!\n", line_count);
 		log_debug2("%d is an input\n", l1);
 		log_assert(!(l1 & 1)); // Inputs can't be inverted
-		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1 >> 1));
 		wire->port_input = true;
+		module->connect(createWireIfNotExists(module, l1), wire);
 		inputs.push_back(wire);
 	}
 
@@ -527,12 +529,14 @@ void AigerReader::parse_aiger_ascii()
 		clk_wire->port_input = true;
 		clk_wire->port_output = false;
 	}
+	digits = ceil(log10(L));
 	for (unsigned i = 0; i < L; ++i, ++line_count) {
 		if (!(f >> l1 >> l2))
 			log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 		log_debug2("%d %d is a latch\n", l1, l2);
 		log_assert(!(l1 & 1));
-		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1));
+		module->connect(createWireIfNotExists(module, l1), q_wire);
 		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
 		if (clk_wire)
@@ -655,12 +659,14 @@ void AigerReader::parse_aiger_binary()
 		clk_wire->port_input = true;
 		clk_wire->port_output = false;
 	}
+	digits = ceil(log10(L));
 	l1 = (I+1) * 2;
 	for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
 		if (!(f >> l2))
 			log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 		log_debug("%d %d is a latch\n", l1, l2);
-		RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+		RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1));
+		module->connect(createWireIfNotExists(module, l1), q_wire);
 		RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
 		if (clk_wire)
-- 
cgit v1.2.3


From 943ea4bf9ea34960bfce517450a8a466d1c54ed3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 08:55:36 -0800
Subject: read_aiger: do not double-count outputs for flops

---
 frontends/aiger/aigerparse.cc | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index bded2bfee..ae16a9e9b 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -756,12 +756,6 @@ void AigerReader::post_process()
 	}
 
 	for (uint32_t i = 0; i < flopNum; i++) {
-		log_assert(co_count < outputs.size());
-		Wire *wire = outputs[co_count++];
-		log_assert(wire);
-		log_assert(wire->port_output);
-		wire->port_output = false;
-
 		RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
 		log_assert(d);
 		log_assert(d->port_output);
-- 
cgit v1.2.3


From d979648b7af4eb5fab042ac55ff2fb40e0c17a89 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 10:02:19 -0800
Subject: read_aiger: more accurate debug message

---
 frontends/aiger/aigerparse.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index ae16a9e9b..b4304a581 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -797,6 +797,7 @@ void AigerReader::post_process()
 						wire->port_input = false;
 						module->connect(wire, existing);
 					}
+					log_debug(" -> %s\n", log_id(escaped_s));
 				}
 				else if (index > 0) {
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@@ -810,8 +811,8 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire->port_input = false;
 					}
+					log_debug(" -> %s\n", log_id(indexed_name));
 				}
-				log_debug(" -> %s\n", log_id(wire));
 			}
 			else if (type == "output") {
 				log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
@@ -833,6 +834,7 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire = existing;
 					}
+					log_debug(" -> %s\n", log_id(escaped_s));
 				}
 				else if (index > 0) {
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@@ -846,8 +848,8 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire->port_output = false;
 					}
+					log_debug(" -> %s\n", log_id(indexed_name));
 				}
-				log_debug(" -> %s\n", log_id(wire));
 				int init;
 				mf >> init;
 				if (init < 2)
-- 
cgit v1.2.3


From 766e16b525d5ab23e451be1e4183cf82560dc8da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 17:34:37 -0800
Subject: read_aiger: make $and/$not/$lut the prefix not suffix

---
 frontends/aiger/aigerparse.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 8a114b18c..6a1b64a21 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	}
 
 	log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-	module->addNotGate(stringf("$%d$not", variable), wire_inv, wire);
+	module->addNotGate(stringf("$not$%d", variable), wire_inv, wire);
 
 	return wire;
 }
@@ -445,10 +445,10 @@ void AigerReader::parse_xaiger()
 					log_assert(o.wire == nullptr);
 					lut_mask[gray] = o.data;
 				}
-				RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID));
+				RTLIL::Cell *output_cell = module->cell(stringf("$and$%d", rootNodeID));
 				log_assert(output_cell);
 				module->remove(output_cell);
-				module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+				module->addLut(stringf("$lut$%d", rootNodeID), input_sig, output_sig, std::move(lut_mask));
 			}
 		}
 		else if (c == 'r') {
@@ -620,7 +620,7 @@ void AigerReader::parse_aiger_ascii()
 		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+		module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
 	}
 	std::getline(f, line); // Ignore up to start of next line
 }
@@ -746,7 +746,7 @@ void AigerReader::parse_aiger_binary()
 		RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 		RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 		RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-		module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
+		module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
 	}
 }
 
-- 
cgit v1.2.3


From ee95fa959acc3a796836c9df970d6739d6cf0ade Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 21:28:27 -0800
Subject: read_aiger: uniquify wires with $aiger<autoidx> prefix

---
 frontends/aiger/aigerparse.cc | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6a1b64a21..859dd5314 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -206,7 +206,7 @@ eval_end:
 };
 
 AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
-	: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
+	: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports), aiger_autoidx(autoidx++)
 {
 	module = new RTLIL::Module;
 	module->name = module_name;
@@ -323,18 +323,18 @@ static uint32_t parse_xaiger_literal(std::istream &f)
 	return from_big_endian(l);
 }
 
-static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
+RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned literal)
 {
 	const unsigned variable = literal >> 1;
 	const bool invert = literal & 1;
-	RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : ""));
+	RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
 	RTLIL::Wire *wire = module->wire(wire_name);
 	if (wire) return wire;
 	log_debug2("Creating %s\n", wire_name.c_str());
 	wire = module->addWire(wire_name);
 	wire->port_input = wire->port_output = false;
 	if (!invert) return wire;
-	RTLIL::IdString wire_inv_name(stringf("$%d", variable));
+	RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
 	RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
 	if (wire_inv) {
 		if (module->cell(wire_inv_name)) return wire;
@@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	}
 
 	log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-	module->addNotGate(stringf("$not$%d", variable), wire_inv, wire);
+	module->addNotGate(stringf("$not$aiger%d$%d", aiger_autoidx, variable), wire_inv, wire);
 
 	return wire;
 }
@@ -422,13 +422,14 @@ void AigerReader::parse_xaiger()
 				uint32_t rootNodeID = parse_xaiger_literal(f);
 				uint32_t cutLeavesM = parse_xaiger_literal(f);
 				log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
-				RTLIL::Wire *output_sig = module->wire(stringf("$%d", rootNodeID));
+				RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
+				log_assert(output_sig);
 				uint32_t nodeID;
 				RTLIL::SigSpec input_sig;
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
-					RTLIL::Wire *wire = module->wire(stringf("$%d", nodeID));
+					RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
 					log_assert(wire);
 					input_sig.append(wire);
 				}
@@ -445,10 +446,10 @@ void AigerReader::parse_xaiger()
 					log_assert(o.wire == nullptr);
 					lut_mask[gray] = o.data;
 				}
-				RTLIL::Cell *output_cell = module->cell(stringf("$and$%d", rootNodeID));
+				RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
 				log_assert(output_cell);
 				module->remove(output_cell);
-				module->addLut(stringf("$lut$%d", rootNodeID), input_sig, output_sig, std::move(lut_mask));
+				module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::move(lut_mask));
 			}
 		}
 		else if (c == 'r') {
-- 
cgit v1.2.3


From 2c65e1abacc4401c4fd3e9b48f52c4de120bc511 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 21:45:27 -0800
Subject: abc9: break SCC by setting (* keep *) on output wires

---
 frontends/aiger/aigerparse.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b4304a581..f4decaf25 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -831,6 +831,7 @@ void AigerReader::post_process()
 					}
 					else {
 						wire->port_output = false;
+						existing->port_output = true;
 						module->connect(wire, existing);
 						wire = existing;
 					}
@@ -845,8 +846,9 @@ void AigerReader::post_process()
 							wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
 					}
 					else {
-						module->connect(wire, existing);
 						wire->port_output = false;
+						existing->port_output = true;
+						module->connect(wire, existing);
 					}
 					log_debug(" -> %s\n", log_id(indexed_name));
 				}
-- 
cgit v1.2.3


From f63f76c372e8003f60565ee109d38ae1797d7e89 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 09:01:53 -0800
Subject: read_aiger: also rename "$0"

---
 frontends/aiger/aigerparse.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 859dd5314..f6b2a639d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -255,7 +255,7 @@ end_of_header:
 	else
 		log_abort();
 
-	RTLIL::Wire* n0 = module->wire("$0");
+	RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
 	if (n0)
 		module->connect(n0, State::S0);
 
@@ -383,7 +383,7 @@ void AigerReader::parse_xaiger()
 	else
 		log_abort();
 
-	RTLIL::Wire* n0 = module->wire("$0");
+	RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
 	if (n0)
 		module->connect(n0, State::S0);
 
-- 
cgit v1.2.3


From 05c8858a907f0f188f1687ede260c2e1a97efe38 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 14:31:32 -0800
Subject: read_aiger: $lut prefix in front

---
 frontends/aiger/aigerparse.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f6b2a639d..a4b1e6fec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1001,9 +1001,9 @@ void AigerReader::post_process()
 		if (cell->type != "$lut") continue;
 		auto y_port = cell->getPort("\\Y").as_bit();
 		if (y_port.wire->width == 1)
-			module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
+			module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
 		else
-			module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
+			module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
 	}
 }
 
-- 
cgit v1.2.3


From 7f728bc116dc804cd944744bbc64ca155028aa22 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 11:16:50 -0800
Subject: read_aiger: ignore constant inputs on LUTs

---
 frontends/aiger/aigerparse.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b5c861936..52bcfa0b6 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -414,6 +414,10 @@ void AigerReader::parse_xaiger()
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
+					if (nodeID < 2) {
+						log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
+						continue;
+					}
 					RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
 					log_assert(wire);
 					input_sig.append(wire);
@@ -421,10 +425,10 @@ void AigerReader::parse_xaiger()
 				// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
 				ce.clear();
 				ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
-				RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
-				for (int j = 0; j < (1 << cutLeavesM); ++j) {
+				RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << GetSize(input_sig));
+				for (int j = 0; j < GetSize(lut_mask); ++j) {
 					int gray = j ^ (j >> 1);
-					ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
+					ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
 					RTLIL::SigBit o(output_sig);
 					bool success YS_ATTRIBUTE(unused) = ce.eval(o);
 					log_assert(success);
-- 
cgit v1.2.3


From cd093c00f84b44662a09d469c2b0d8ba6ecf6f6e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 11:56:01 -0800
Subject: read_aiger: discard LUT inputs with nodeID == 0; not < 2

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 52bcfa0b6..e7478c316 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -414,7 +414,7 @@ void AigerReader::parse_xaiger()
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
-					if (nodeID < 2) {
+					if (nodeID == 0) {
 						log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
 						continue;
 					}
-- 
cgit v1.2.3


From 73526a6f103c927dd0d1504281659a87e7943688 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Jan 2020 14:21:25 -0800
Subject: read_aiger: also parse abc9_mergeability

---
 frontends/aiger/aigerparse.cc | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e7478c316..b9c648afd 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -442,11 +442,13 @@ void AigerReader::parse_xaiger()
 			}
 		}
 		else if (c == 'r') {
-			uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			uint32_t dataSize = parse_xaiger_literal(f);
 			flopNum = parse_xaiger_literal(f);
 			log_debug("flopNum = %u\n", flopNum);
 			log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
-			f.ignore(flopNum * sizeof(uint32_t));
+			mergeability.reserve(flopNum);
+			for (unsigned i = 0; i < flopNum; i++)
+				mergeability.emplace_back(parse_xaiger_literal(f));
 		}
 		else if (c == 'n') {
 			parse_xaiger_literal(f);
@@ -774,6 +776,7 @@ void AigerReader::post_process()
 		auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
 		ff->setPort("\\D", d);
 		ff->setPort("\\Q", q);
+		ff->attributes["\\abc9_mergeability"] = mergeability[i];
 	}
 
 	dict<RTLIL::IdString, int> wideports_cache;
-- 
cgit v1.2.3


From c7fbe13db5144cf87c56d3f7a620a295029606b3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 Jan 2020 13:11:43 -0800
Subject: read_aiger: set abc9_box_seq attr

---
 frontends/aiger/aigerparse.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index b9c648afd..418fd722c 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -478,6 +478,7 @@ void AigerReader::parse_xaiger()
 				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
 				cell->setPort("\\i", SigSpec(State::S0, boxInputs));
 				cell->setPort("\\o", SigSpec(State::S0, boxOutputs));
+				cell->attributes["\\abc9_box_seq"] = oldBoxNum;
 				boxes.emplace_back(cell);
 			}
 		}
-- 
cgit v1.2.3


From ce6a690d27f3ce3b637f1d9be42b1efd744500d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 12:29:07 -0800
Subject: xilinx/ice40/ecp5: undo permuting LUT masks in lut_map

Now done in read_aiger
---
 frontends/aiger/aigerparse.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 418fd722c..f92a11c6d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -410,7 +410,7 @@ void AigerReader::parse_xaiger()
 				RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
 				log_assert(output_sig);
 				uint32_t nodeID;
-				RTLIL::SigSpec input_sig;
+				std::vector<SigBit> input_bits;
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
@@ -420,8 +420,10 @@ void AigerReader::parse_xaiger()
 					}
 					RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
 					log_assert(wire);
-					input_sig.append(wire);
+					input_bits.push_back(wire);
 				}
+				// Reverse input order as fastest input is returned first
+				RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend()));
 				// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
 				ce.clear();
 				ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
-- 
cgit v1.2.3


From 6d27d4372730cb94306a4f314482459f9d527d7c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 Jan 2020 10:37:16 -0800
Subject: Add and use SigSpec::reverse()

---
 frontends/aiger/aigerparse.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'frontends/aiger/aigerparse.cc')

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f92a11c6d..a42569301 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -410,7 +410,7 @@ void AigerReader::parse_xaiger()
 				RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
 				log_assert(output_sig);
 				uint32_t nodeID;
-				std::vector<SigBit> input_bits;
+				RTLIL::SigSpec input_sig;
 				for (unsigned j = 0; j < cutLeavesM; ++j) {
 					nodeID = parse_xaiger_literal(f);
 					log_debug2("\t%u\n", nodeID);
@@ -420,10 +420,10 @@ void AigerReader::parse_xaiger()
 					}
 					RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
 					log_assert(wire);
-					input_bits.push_back(wire);
+					input_sig.append(wire);
 				}
 				// Reverse input order as fastest input is returned first
-				RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend()));
+				input_sig.reverse();
 				// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
 				ce.clear();
 				ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
-- 
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