From aa25a4cec66bfde84f9142b21679e82ba90ee910 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Aug 2016 19:27:42 +0200
Subject: Added $anyconst support to yosys-smtbmc

---
 examples/smtbmc/.gitignore |  3 +++
 examples/smtbmc/Makefile   |  9 ++++++++-
 examples/smtbmc/demo5.v    | 18 ++++++++++++++++++
 3 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 examples/smtbmc/demo5.v

(limited to 'examples')

diff --git a/examples/smtbmc/.gitignore b/examples/smtbmc/.gitignore
index fbddafa8a..88d264c63 100644
--- a/examples/smtbmc/.gitignore
+++ b/examples/smtbmc/.gitignore
@@ -13,3 +13,6 @@ demo3.yslog
 demo4.smt2
 demo4.vcd
 demo4.yslog
+demo5.smt2
+demo5.vcd
+demo5.yslog
diff --git a/examples/smtbmc/Makefile b/examples/smtbmc/Makefile
index 6078fc64f..a2d4f444b 100644
--- a/examples/smtbmc/Makefile
+++ b/examples/smtbmc/Makefile
@@ -16,6 +16,9 @@ demo3: demo3.smt2
 demo4: demo4.smt2
 	yosys-smtbmc -s yices --dump-vcd demo4.vcd --smtc demo4.smtc demo4.smt2
 
+demo5: demo5.smt2
+	yosys-smtbmc -g -t 50 --dump-vcd demo5.vcd demo5.smt2
+
 demo1.smt2: demo1.v
 	yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2'
 
@@ -28,11 +31,15 @@ demo3.smt2: demo3.v
 demo4.smt2: demo4.v
 	yosys -ql demo4.yslog -p 'read_verilog -formal demo4.v; prep -top demo4 -nordff; write_smt2 -wires demo4.smt2'
 
+demo5.smt2: demo5.v
+	yosys -ql demo5.yslog -p 'read_verilog -formal demo5.v; prep -top demo5 -nordff; write_smt2 -wires demo5.smt2'
+
 clean:
 	rm -f demo1.yslog demo1.smt2 demo1.vcd
 	rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
 	rm -f demo3.yslog demo3.smt2 demo3.vcd
 	rm -f demo4.yslog demo4.smt2 demo4.vcd
+	rm -f demo5.yslog demo5.smt2 demo5.vcd
 
-.PHONY: demo1 demo2 demo3 demo4 clean
+.PHONY: demo1 demo2 demo3 demo4 demo5 clean
 
diff --git a/examples/smtbmc/demo5.v b/examples/smtbmc/demo5.v
new file mode 100644
index 000000000..63ace307c
--- /dev/null
+++ b/examples/smtbmc/demo5.v
@@ -0,0 +1,18 @@
+// Demo for $anyconst
+
+module demo5 (input clk);
+	wire [7:0] step_size = $anyconst;
+	reg [7:0] state = 0, count = 0;
+	reg [31:0] hash = 0;
+
+	always @(posedge clk) begin
+		count <= count + 1;
+		hash <= ((hash << 5) + hash) ^ state;
+		state <= state + step_size;
+	end
+
+	always @* begin
+		if (count == 42)
+			assert(hash == 32'h A18FAC0A);
+	end
+endmodule
-- 
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