From f589ce86bac3169281a077248af328f6758ff0eb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 Jan 2019 17:02:01 +0100 Subject: Add skeleton Yosys-Libero igloo2 example project Signed-off-by: Clifford Wolf --- examples/igloo2/.gitignore | 2 ++ examples/igloo2/example.v | 22 ++++++++++++++++++++++ examples/igloo2/example.ys | 2 ++ examples/igloo2/libero.sh | 4 ++++ examples/igloo2/libero.tcl | 14 ++++++++++++++ 5 files changed, 44 insertions(+) create mode 100644 examples/igloo2/.gitignore create mode 100644 examples/igloo2/example.v create mode 100644 examples/igloo2/example.ys create mode 100644 examples/igloo2/libero.sh create mode 100644 examples/igloo2/libero.tcl (limited to 'examples/igloo2') diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore new file mode 100644 index 000000000..ae86e69cc --- /dev/null +++ b/examples/igloo2/.gitignore @@ -0,0 +1,2 @@ +/example.edn +/work diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v new file mode 100644 index 000000000..3eb7007c5 --- /dev/null +++ b/examples/igloo2/example.v @@ -0,0 +1,22 @@ +module top ( + input clk, + output LED1, + output LED2, + output LED3, + output LED4, + output LED5 +); + + localparam BITS = 5; + localparam LOG2DELAY = 22; + + reg [BITS+LOG2DELAY-1:0] counter = 0; + reg [BITS-1:0] outcnt; + + always @(posedge clk) begin + counter <= counter + 1; + outcnt <= counter >> LOG2DELAY; + end + + assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); +endmodule diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys new file mode 100644 index 000000000..75a305d86 --- /dev/null +++ b/examples/igloo2/example.ys @@ -0,0 +1,2 @@ +read_verilog example.v +synth_sf2 -top top -edif example.edn diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh new file mode 100644 index 000000000..582f6ccb9 --- /dev/null +++ b/examples/igloo2/libero.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -ex +rm -rf work +LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl new file mode 100644 index 000000000..cc1ab2403 --- /dev/null +++ b/examples/igloo2/libero.tcl @@ -0,0 +1,14 @@ +# Run with "libero SCRIPT:libero.tcl" + +new_project \ + -name top \ + -location work \ + -family IGLOO2 \ + -die PA4MGL500 \ + -package tq144 \ + -speed -1 \ + -hdl VERILOG + +import_files -edif {example.edn} +run_tool –name {COMPILE} +run_tool –name {PLACEROUTEN} -- cgit v1.2.3 From 2a2e0a4722ded7628b71f436b94a06aebd57bb62 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 8 Jan 2019 20:16:36 +0100 Subject: Improve igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/.gitignore | 3 ++- examples/igloo2/example.ys | 3 ++- examples/igloo2/libero.sh | 4 ---- examples/igloo2/libero.tcl | 27 ++++++++++++++++++++++++--- examples/igloo2/runme.sh | 5 +++++ 5 files changed, 33 insertions(+), 9 deletions(-) delete mode 100644 examples/igloo2/libero.sh create mode 100644 examples/igloo2/runme.sh (limited to 'examples/igloo2') diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore index ae86e69cc..fa3c3d7ed 100644 --- a/examples/igloo2/.gitignore +++ b/examples/igloo2/.gitignore @@ -1,2 +1,3 @@ -/example.edn +/netlist.edn +/netlist.v /work diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys index 75a305d86..872f97b99 100644 --- a/examples/igloo2/example.ys +++ b/examples/igloo2/example.ys @@ -1,2 +1,3 @@ read_verilog example.v -synth_sf2 -top top -edif example.edn +synth_sf2 -top top -edif netlist.edn +write_verilog netlist.v diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh deleted file mode 100644 index 582f6ccb9..000000000 --- a/examples/igloo2/libero.sh +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/bash -set -ex -rm -rf work -LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index cc1ab2403..9f6d3b792 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -9,6 +9,27 @@ new_project \ -speed -1 \ -hdl VERILOG -import_files -edif {example.edn} -run_tool –name {COMPILE} -run_tool –name {PLACEROUTEN} +# import_files -edif "[pwd]/netlist.edn" + +import_files -hdl_source "[pwd]/netlist.v" +set_root top + +save_project + +puts "**> SYNTHESIZE" +run_tool -name {SYNTHESIZE} +puts "<** SYNTHESIZE" + +puts "**> COMPILE" +run_tool -name {COMPILE} +puts "<** COMPILE" + +puts "**> PLACEROUTE" +run_tool -name {PLACEROUTE} +puts "<** PLACEROUTE" + +# puts "**> export_bitstream" +# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} +# puts "<** export_bitstream" + +exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh new file mode 100644 index 000000000..4edfb5409 --- /dev/null +++ b/examples/igloo2/runme.sh @@ -0,0 +1,5 @@ +#!/bin/bash +set -ex +rm -rf work +yosys example.ys +LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl -- cgit v1.2.3 From 9b277fc21ea455a0e0ca9b7acde039e90ddb380d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jan 2019 13:35:52 +0100 Subject: Improve Igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/.gitignore | 4 ++-- examples/igloo2/example.fp.pdc | 0 examples/igloo2/example.io.pdc | 0 examples/igloo2/example.sdc | 0 examples/igloo2/example.v | 2 +- examples/igloo2/example.ys | 4 ++-- examples/igloo2/libero.tcl | 50 +++++++++++++++++++++++++++++------------- examples/igloo2/runme.sh | 3 +-- 8 files changed, 41 insertions(+), 22 deletions(-) create mode 100644 examples/igloo2/example.fp.pdc create mode 100644 examples/igloo2/example.io.pdc create mode 100644 examples/igloo2/example.sdc (limited to 'examples/igloo2') diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore index fa3c3d7ed..ea58efc9f 100644 --- a/examples/igloo2/.gitignore +++ b/examples/igloo2/.gitignore @@ -1,3 +1,3 @@ /netlist.edn -/netlist.v -/work +/netlist.vm +/proj diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc new file mode 100644 index 000000000..e69de29bb diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 3eb7007c5..0e336e557 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,4 +1,4 @@ -module top ( +module example ( input clk, output LED1, output LED2, diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys index 872f97b99..04ea02672 100644 --- a/examples/igloo2/example.ys +++ b/examples/igloo2/example.ys @@ -1,3 +1,3 @@ read_verilog example.v -synth_sf2 -top top -edif netlist.edn -write_verilog netlist.v +synth_sf2 -top example -edif netlist.edn +write_verilog netlist.vm diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 9f6d3b792..b2090f402 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -1,24 +1,38 @@ # Run with "libero SCRIPT:libero.tcl" +file delete -force proj + new_project \ - -name top \ - -location work \ + -name example \ + -location proj \ + -block_mode 1 \ + -hdl "VERILOG" \ -family IGLOO2 \ -die PA4MGL500 \ -package tq144 \ - -speed -1 \ - -hdl VERILOG - -# import_files -edif "[pwd]/netlist.edn" - -import_files -hdl_source "[pwd]/netlist.v" -set_root top - -save_project - -puts "**> SYNTHESIZE" -run_tool -name {SYNTHESIZE} -puts "<** SYNTHESIZE" + -speed -1 + +import_files -hdl_source {netlist.vm} +import_files -sdc {example.sdc} +import_files -io_pdc {example.io.pdc} +import_files -fp_pdc {example.fp.pdc} +set_option -synth 0 + +organize_tool_files -tool PLACEROUTE \ + -file {proj/constraint/example.sdc} \ + -file {proj/constraint/io/example.io.pdc} \ + -file {proj/constraint/fp/example.fp.pdc} \ + -input_type constraint + +organize_tool_files -tool VERIFYTIMING \ + -file {proj/constraint/example.sdc} \ + -input_type constraint + +configure_tool -name PLACEROUTE \ + -params TDPR:true \ + -params PDPR:false \ + -params EFFORT_LEVEL:false \ + -params REPAIR_MIN_DELAY:false puts "**> COMPILE" run_tool -name {COMPILE} @@ -28,6 +42,12 @@ puts "**> PLACEROUTE" run_tool -name {PLACEROUTE} puts "<** PLACEROUTE" +puts "**> VERIFYTIMING" +run_tool -name {VERIFYTIMING} +puts "<** VERIFYTIMING" + +save_project + # puts "**> export_bitstream" # export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} # puts "<** export_bitstream" diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 4edfb5409..54247759f 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,5 +1,4 @@ #!/bin/bash set -ex -rm -rf work -yosys example.ys +yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl -- cgit v1.2.3 From db5765b443c26b5b2dc3ac56d5a448fc8b861d43 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jan 2019 14:38:37 +0100 Subject: Add SF2 IO buffer insertion Signed-off-by: Clifford Wolf --- examples/igloo2/example.v | 3 ++- examples/igloo2/libero.tcl | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'examples/igloo2') diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 0e336e557..1a1967d5a 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,5 +1,6 @@ module example ( input clk, + input EN, output LED1, output LED2, output LED3, @@ -14,7 +15,7 @@ module example ( reg [BITS-1:0] outcnt; always @(posedge clk) begin - counter <= counter + 1; + counter <= counter + EN; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index b2090f402..952342a4c 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -5,7 +5,7 @@ file delete -force proj new_project \ -name example \ -location proj \ - -block_mode 1 \ + -block_mode 0 \ -hdl "VERILOG" \ -family IGLOO2 \ -die PA4MGL500 \ -- cgit v1.2.3 From f3556e9f7ac6947be440a51699af773655de4911 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jan 2019 14:54:04 +0100 Subject: Cleanups in igloo2 example design Signed-off-by: Clifford Wolf --- examples/igloo2/example.fp.pdc | 0 examples/igloo2/example.io.pdc | 0 examples/igloo2/example.pdc | 1 + examples/igloo2/example.sdc | 1 + examples/igloo2/example.ys | 3 --- examples/igloo2/libero.tcl | 6 ++---- 6 files changed, 4 insertions(+), 7 deletions(-) delete mode 100644 examples/igloo2/example.fp.pdc delete mode 100644 examples/igloo2/example.io.pdc create mode 100644 examples/igloo2/example.pdc delete mode 100644 examples/igloo2/example.ys (limited to 'examples/igloo2') diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc deleted file mode 100644 index e69de29bb..000000000 diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc deleted file mode 100644 index e69de29bb..000000000 diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc new file mode 100644 index 000000000..e6ffd53db --- /dev/null +++ b/examples/igloo2/example.pdc @@ -0,0 +1 @@ +# Add placement constraints here diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc index e69de29bb..c6ff94161 100644 --- a/examples/igloo2/example.sdc +++ b/examples/igloo2/example.sdc @@ -0,0 +1 @@ +# Add timing constraints here diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys deleted file mode 100644 index 04ea02672..000000000 --- a/examples/igloo2/example.ys +++ /dev/null @@ -1,3 +0,0 @@ -read_verilog example.v -synth_sf2 -top example -edif netlist.edn -write_verilog netlist.vm diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 952342a4c..1f3476316 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -14,14 +14,12 @@ new_project \ import_files -hdl_source {netlist.vm} import_files -sdc {example.sdc} -import_files -io_pdc {example.io.pdc} -import_files -fp_pdc {example.fp.pdc} +import_files -io_pdc {example.pdc} set_option -synth 0 organize_tool_files -tool PLACEROUTE \ -file {proj/constraint/example.sdc} \ - -file {proj/constraint/io/example.io.pdc} \ - -file {proj/constraint/fp/example.fp.pdc} \ + -file {proj/constraint/io/example.pdc} \ -input_type constraint organize_tool_files -tool VERIFYTIMING \ -- cgit v1.2.3