From b34385ec924b6067c1f82bdbae923f8062518956 Mon Sep 17 00:00:00 2001
From: Uros Platise <uros@isotel.eu>
Date: Sat, 5 Mar 2016 08:34:05 +0100
Subject: Completed ngspice digital example with verilog tb

---
 examples/cmos/README | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 examples/cmos/README

(limited to 'examples/cmos/README')

diff --git a/examples/cmos/README b/examples/cmos/README
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+
+In this directory you will find out, how to generate a spice output
+operating in two modes, analog or event-driven mode supported by ngspice
+xspice sub-module.
+
+Each test bench can be run separately by either running:
+
+- testbench.sh, to start analog simulation or
+- testbench_digital.sh for mixed-signal digital simulation.
+
+The later case also includes pure verilog simulation using the iverilog
+and gtkwave to represent the results.
-- 
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