From beedaa58561eb7cabf24e0d267beb77d5c78ef1d Mon Sep 17 00:00:00 2001
From: japm48 <japm48@users.noreply.github.com>
Date: Sun, 22 Jul 2018 22:29:31 +0200
Subject: fix basys3 example

Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.

Added `open_hw` needed for programming.
---
 examples/basys3/example.xdc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'examples/basys3/example.xdc')

diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc
index c1fd0e925..8cdaa1996 100644
--- a/examples/basys3/example.xdc
+++ b/examples/basys3/example.xdc
@@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
 
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
 
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
-- 
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