From 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 Mon Sep 17 00:00:00 2001 From: Kali Prasad Date: Mon, 4 Mar 2019 23:26:56 +0530 Subject: Added examples/anlogic/ --- examples/anlogic/demo.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 examples/anlogic/demo.v (limited to 'examples/anlogic/demo.v') diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..a7edf4e37 --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule \ No newline at end of file -- cgit v1.2.3 From 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e Mon Sep 17 00:00:00 2001 From: Kali Prasad Date: Wed, 6 Mar 2019 09:51:11 +0530 Subject: examples/anlogic/ now also output the SVF file. --- examples/anlogic/demo.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'examples/anlogic/demo.v') diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v index a7edf4e37..e17db771e 100644 --- a/examples/anlogic/demo.v +++ b/examples/anlogic/demo.v @@ -1,18 +1,18 @@ module demo ( - input wire CLK_IN, - output wire R_LED + input wire CLK_IN, + output wire R_LED ); parameter time1 = 30'd12_000_000; reg led_state; reg [29:0] count; - + always @(posedge CLK_IN)begin if(count == time1)begin - count<= 30'd0; + count<= 30'd0; led_state <= ~led_state; end else count <= count + 1'b1; end assign R_LED = led_state; -endmodule \ No newline at end of file +endmodule -- cgit v1.2.3