From c340fbfab23c582103402bbd812d9bca4510dc41 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 21:58:04 -0700
Subject: Force $inout.out ports to begin with '$' to indicate internal

---
 backends/aiger/xaiger.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends')

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cbce4c83b..21b281708 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -424,7 +424,7 @@ struct XAigerWriter
 			// inherit existing inout's drivers
 			if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
 					|| keep_bits.count(bit)) {
-				RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
+				RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
 				RTLIL::Wire *new_wire = module->wire(wire_name);
 				if (!new_wire)
 					new_wire = module->addWire(wire_name, GetSize(wire));
-- 
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