From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- backends/blif/blif.cc | 4 ++-- backends/edif/edif.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'backends') diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 90d1b3fc4..edb6809ee 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -118,7 +118,7 @@ struct BlifDumper for (auto &it : inputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i))); + fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i))); } fprintf(f, "\n"); @@ -126,7 +126,7 @@ struct BlifDumper for (auto &it : outputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i))); + fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i))); } fprintf(f, "\n"); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index bb2b26e26..f003c750d 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -271,7 +271,7 @@ struct EdifBackend : public Backend { } else { fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i)); + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } -- cgit v1.2.3