From 6f4f795953b2a38ec77984c7e1b50f579b59272e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 15 Apr 2020 12:15:36 -0700 Subject: aiger/xaiger: use odd for negedge clk, even for posedge Since abc9 doesn't like negative mergeability values --- backends/aiger/xaiger.cc | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index b8d65de4e..e2d8e1e7f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -627,21 +627,25 @@ struct XAigerWriter write_s_buffer(ff_bits.size()); dict clk_to_mergeability; + for (const auto &i : ff_bits) { + const Cell *cell = i.second; + log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_))); + + SigBit clock = sigmap(cell->getPort(ID::C)); + clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1)); + } for (const auto &i : ff_bits) { const SigBit &d = i.first; const Cell *cell = i.second; - log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_))); - SigBit clock = sigmap(cell->getPort(ID::C)); - auto r = clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size() + 1)); - int mergeability = r.first->second; + int mergeability = clk_to_mergeability.at(clock); log_assert(mergeability > 0); if (cell->type == ID($_DFF_N_)) - write_r_buffer(-mergeability); - else if (cell->type == ID($_DFF_P_)) write_r_buffer(mergeability); + else if (cell->type == ID($_DFF_P_)) + write_r_buffer(mergeability+1); else log_abort(); SigBit Q = sigmap(cell->getPort(ID::Q)); -- cgit v1.2.3