From 03500748192dc93583c0e0f95640865603650714 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Aug 2015 11:27:19 +0200 Subject: Re-created command-reference-manual.tex, copied some doc fixes to online help --- backends/verilog/verilog_backend.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e6a86a16a..28c54ce0b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1315,14 +1315,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } struct VerilogBackend : public Backend { - VerilogBackend() : Backend("verilog", "write design to verilog file") { } + VerilogBackend() : Backend("verilog", "write design to Verilog file") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" write_verilog [options] [filename]\n"); log("\n"); - log("Write the current design to a verilog file.\n"); + log("Write the current design to a Verilog file.\n"); log("\n"); log(" -norename\n"); log(" without this option all internal object names (the ones with a dollar\n"); @@ -1336,7 +1336,7 @@ struct VerilogBackend : public Backend { log(" with this option attributes are included as comments in the output\n"); log("\n"); log(" -noexpr\n"); - log(" without this option all internal cells are converted to verilog\n"); + log(" without this option all internal cells are converted to Verilog\n"); log(" expressions.\n"); log("\n"); log(" -blackboxes\n"); -- cgit v1.2.3