From 0c67393313f125b6fca70614f10c2ec61116dd82 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 01:56:16 +0200 Subject: Added support for $bu0 to verilog backend --- backends/verilog/verilog_backend.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d7fe4c4e2..6be26329a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -581,6 +581,22 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$bu0") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->connections["\\Y"]); + if (cell->parameters["\\A_SIGNED"].as_bool()) { + fprintf(f, " = $signed("); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, ");\n"); + } else { + fprintf(f, " = { 1'b0, "); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, " };\n"); + } + return true; + } + if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); -- cgit v1.2.3 From a30e2857c730c1adc1c6af2c995059af904eec0b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 02:16:30 +0200 Subject: Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend --- backends/verilog/verilog_backend.cc | 38 ++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6be26329a..80ad7cb90 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -533,16 +533,18 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { int width = cell->parameters["\\WIDTH"].as_int(); int s_width = cell->connections["\\S"].width; - std::string reg_name = cellname(cell); - fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), width-1, reg_name.c_str()); + std::string func_name = cellname(cell); - dump_attributes(f, indent, cell->attributes); + fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); + fprintf(f, "%s" " input [%d:0] a;\n", indent.c_str(), width-1); + fprintf(f, "%s" " input [%d:0] b;\n", indent.c_str(), s_width*width-1); + fprintf(f, "%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); + + dump_attributes(f, indent + " ", cell->attributes); if (!noattr) - fprintf(f, "%s" "(* parallel_case *)\n", indent.c_str()); - fprintf(f, "%s" "always @*\n", indent.c_str()); - fprintf(f, "%s" " casez (", indent.c_str()); - dump_sigspec(f, cell->connections["\\S"]); - fprintf(f, noattr ? ") // synopsys parallel_case\n" : ")\n"); + fprintf(f, "%s" " (* parallel_case *)\n", indent.c_str()); + fprintf(f, "%s" " casez (s)", indent.c_str()); + fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); for (int i = 0; i < s_width; i++) { @@ -552,22 +554,24 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%c", j == i ? '1' : cell->type == "$pmux_safe" ? '0' : '?'); fprintf(f, ":\n"); - fprintf(f, "%s" " %s = ", indent.c_str(), reg_name.c_str()); - - RTLIL::SigSpec s = cell->connections["\\B"].extract(i * width, width); - dump_sigspec(f, s); - fprintf(f, ";\n"); + fprintf(f, "%s" " %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width); } fprintf(f, "%s" " default:\n", indent.c_str()); - fprintf(f, "%s" " %s = ", indent.c_str(), reg_name.c_str()); - dump_sigspec(f, cell->connections["\\A"]); - fprintf(f, ";\n"); + fprintf(f, "%s" " %s = a;\n", indent.c_str(), func_name.c_str()); fprintf(f, "%s" " endcase\n", indent.c_str()); + fprintf(f, "%s" "endfunction\n", indent.c_str()); + fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->connections["\\Y"]); - fprintf(f, " = %s;\n", reg_name.c_str()); + fprintf(f, " = %s(", func_name.c_str()); + dump_sigspec(f, cell->connections["\\A"]); + fprintf(f, ", "); + dump_sigspec(f, cell->connections["\\B"]); + fprintf(f, ", "); + dump_sigspec(f, cell->connections["\\S"]); + fprintf(f, ");\n"); return true; } -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- backends/verilog/verilog_backend.cc | 58 ++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 80ad7cb90..6aeb5084b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -134,17 +134,17 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { sig.optimize(); - if (sig.chunks.size() != 1 || sig.chunks[0].wire == NULL) + if (sig.__chunks.size() != 1 || sig.__chunks[0].wire == NULL) return false; - if (reg_wires.count(sig.chunks[0].wire->name) == 0) + if (reg_wires.count(sig.__chunks[0].wire->name) == 0) return false; - reg_name = id(sig.chunks[0].wire->name); - if (sig.width != sig.chunks[0].wire->width) { - if (sig.width == 1) - reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset); + reg_name = id(sig.__chunks[0].wire->name); + if (sig.__width != sig.__chunks[0].wire->width) { + if (sig.__width == 1) + reg_name += stringf("[%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); else - reg_name += stringf("[%d:%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset + sig.chunks[0].width - 1, - sig.chunks[0].wire->start_offset + sig.chunks[0].offset); + reg_name += stringf("[%d:%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset + sig.__chunks[0].width - 1, + sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); } return true; } @@ -221,12 +221,12 @@ void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false) void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) { - if (sig.chunks.size() == 1) { - dump_sigchunk(f, sig.chunks[0]); + if (sig.__chunks.size() == 1) { + dump_sigchunk(f, sig.__chunks[0]); } else { fprintf(f, "{ "); - for (auto it = sig.chunks.rbegin(); it != sig.chunks.rend(); it++) { - if (it != sig.chunks.rbegin()) + for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) { + if (it != sig.__chunks.rbegin()) fprintf(f, ", "); dump_sigchunk(f, *it, true); } @@ -300,11 +300,11 @@ std::string cellname(RTLIL::Cell *cell) if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0) { RTLIL::SigSpec sig = cell->connections["\\Q"]; - if (sig.width != 1 || sig.is_fully_const()) + if (sig.__width != 1 || sig.is_fully_const()) goto no_special_reg_name; sig.optimize(); - RTLIL::Wire *wire = sig.chunks[0].wire; + RTLIL::Wire *wire = sig.__chunks[0].wire; if (wire->name[0] != '\\') goto no_special_reg_name; @@ -318,7 +318,7 @@ std::string cellname(RTLIL::Cell *cell) cell_name = cell_name + "_reg"; if (wire->width != 1) - cell_name += stringf("[%d]", wire->start_offset + sig.chunks[0].offset); + cell_name += stringf("[%d]", wire->start_offset + sig.__chunks[0].offset); if (active_module && active_module->count_id(cell_name) > 0) goto no_special_reg_name; @@ -532,7 +532,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections["\\S"].width; + int s_width = cell->connections["\\S"].__width; std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -725,7 +725,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, ","); first_arg = false; fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); - if (it->second.width > 0) + if (it->second.__width > 0) dump_sigspec(f, it->second); fprintf(f, ")"); } @@ -751,7 +751,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - if (it->first.width == 0) + if (it->first.__width == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -772,7 +772,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw) { - if (sw->signal.width == 0) { + if (sw->signal.__width == 0) { fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) { if ((*it)->compare.size() == 0) @@ -811,9 +811,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs) case_body_find_regs(*it2); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - for (size_t i = 0; i < it->first.chunks.size(); i++) - if (it->first.chunks[i].wire) - reg_wires.insert(it->first.chunks[i].wire->name); + for (size_t i = 0; i < it->first.__chunks.size(); i++) + if (it->first.__chunks[i].wire) + reg_wires.insert(it->first.__chunks[i].wire->name); } } @@ -823,9 +823,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r case_body_find_regs(&proc->root_case); for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++) for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) { - for (size_t i = 0; i < it2->first.chunks.size(); i++) - if (it2->first.chunks[i].wire) - reg_wires.insert(it2->first.chunks[i].wire->name); + for (size_t i = 0; i < it2->first.__chunks.size(); i++) + if (it2->first.__chunks[i].wire) + reg_wires.insert(it2->first.__chunks[i].wire->name); } return; } @@ -876,7 +876,7 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r } for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) { - if (it->first.width == 0) + if (it->first.__width == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -911,9 +911,9 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) RTLIL::SigSpec sig = cell->connections["\\Q"]; sig.optimize(); - if (sig.chunks.size() == 1 && sig.chunks[0].wire) - for (int i = 0; i < sig.chunks[0].width; i++) - reg_bits.insert(std::pair(sig.chunks[0].wire, sig.chunks[0].offset+i)); + if (sig.__chunks.size() == 1 && sig.__chunks[0].wire) + for (int i = 0; i < sig.__chunks[0].width; i++) + reg_bits.insert(std::pair(sig.__chunks[0].wire, sig.__chunks[0].offset+i)); } for (auto &it : module->wires) { -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- backends/verilog/verilog_backend.cc | 58 ++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6aeb5084b..4b60f0fbd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -134,17 +134,17 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { sig.optimize(); - if (sig.__chunks.size() != 1 || sig.__chunks[0].wire == NULL) + if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) return false; - if (reg_wires.count(sig.__chunks[0].wire->name) == 0) + if (reg_wires.count(sig.chunks()[0].wire->name) == 0) return false; - reg_name = id(sig.__chunks[0].wire->name); - if (sig.__width != sig.__chunks[0].wire->width) { - if (sig.__width == 1) - reg_name += stringf("[%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); + reg_name = id(sig.chunks()[0].wire->name); + if (sig.size() != sig.chunks()[0].wire->width) { + if (sig.size() == 1) + reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); else - reg_name += stringf("[%d:%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset + sig.__chunks[0].width - 1, - sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); + reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1, + sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); } return true; } @@ -221,12 +221,12 @@ void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false) void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) { - if (sig.__chunks.size() == 1) { - dump_sigchunk(f, sig.__chunks[0]); + if (sig.chunks().size() == 1) { + dump_sigchunk(f, sig.chunks()[0]); } else { fprintf(f, "{ "); - for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) { - if (it != sig.__chunks.rbegin()) + for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { + if (it != sig.chunks().rbegin()) fprintf(f, ", "); dump_sigchunk(f, *it, true); } @@ -300,11 +300,11 @@ std::string cellname(RTLIL::Cell *cell) if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0) { RTLIL::SigSpec sig = cell->connections["\\Q"]; - if (sig.__width != 1 || sig.is_fully_const()) + if (sig.size() != 1 || sig.is_fully_const()) goto no_special_reg_name; sig.optimize(); - RTLIL::Wire *wire = sig.__chunks[0].wire; + RTLIL::Wire *wire = sig.chunks()[0].wire; if (wire->name[0] != '\\') goto no_special_reg_name; @@ -318,7 +318,7 @@ std::string cellname(RTLIL::Cell *cell) cell_name = cell_name + "_reg"; if (wire->width != 1) - cell_name += stringf("[%d]", wire->start_offset + sig.__chunks[0].offset); + cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset); if (active_module && active_module->count_id(cell_name) > 0) goto no_special_reg_name; @@ -532,7 +532,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections["\\S"].__width; + int s_width = cell->connections["\\S"].size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -725,7 +725,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, ","); first_arg = false; fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); - if (it->second.__width > 0) + if (it->second.size() > 0) dump_sigspec(f, it->second); fprintf(f, ")"); } @@ -751,7 +751,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - if (it->first.__width == 0) + if (it->first.size() == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -772,7 +772,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) { if ((*it)->compare.size() == 0) @@ -811,9 +811,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs) case_body_find_regs(*it2); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - for (size_t i = 0; i < it->first.__chunks.size(); i++) - if (it->first.__chunks[i].wire) - reg_wires.insert(it->first.__chunks[i].wire->name); + for (size_t i = 0; i < it->first.chunks().size(); i++) + if (it->first.chunks()[i].wire) + reg_wires.insert(it->first.chunks()[i].wire->name); } } @@ -823,9 +823,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r case_body_find_regs(&proc->root_case); for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++) for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) { - for (size_t i = 0; i < it2->first.__chunks.size(); i++) - if (it2->first.__chunks[i].wire) - reg_wires.insert(it2->first.__chunks[i].wire->name); + for (size_t i = 0; i < it2->first.chunks().size(); i++) + if (it2->first.chunks()[i].wire) + reg_wires.insert(it2->first.chunks()[i].wire->name); } return; } @@ -876,7 +876,7 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r } for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) { - if (it->first.__width == 0) + if (it->first.size() == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -911,9 +911,9 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) RTLIL::SigSpec sig = cell->connections["\\Q"]; sig.optimize(); - if (sig.__chunks.size() == 1 && sig.__chunks[0].wire) - for (int i = 0; i < sig.__chunks[0].width; i++) - reg_bits.insert(std::pair(sig.__chunks[0].wire, sig.__chunks[0].offset+i)); + if (sig.chunks().size() == 1 && sig.chunks()[0].wire) + for (int i = 0; i < sig.chunks()[0].width; i++) + reg_bits.insert(std::pair(sig.chunks()[0].wire, sig.chunks()[0].offset+i)); } for (auto &it : module->wires) { -- cgit v1.2.3 From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:58:44 +0200 Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() --- backends/verilog/verilog_backend.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 4b60f0fbd..160835087 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -149,7 +149,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) return true; } -void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) +void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) { if (width < 0) width = data.bits.size() - offset; @@ -203,7 +203,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo } } -void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false) +void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal); -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- backends/verilog/verilog_backend.cc | 3 --- 1 file changed, 3 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 160835087..1dcc3003a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -133,7 +133,6 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { - sig.optimize(); if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) return false; if (reg_wires.count(sig.chunks()[0].wire->name) == 0) @@ -303,7 +302,6 @@ std::string cellname(RTLIL::Cell *cell) if (sig.size() != 1 || sig.is_fully_const()) goto no_special_reg_name; - sig.optimize(); RTLIL::Wire *wire = sig.chunks()[0].wire; if (wire->name[0] != '\\') @@ -909,7 +907,6 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) continue; RTLIL::SigSpec sig = cell->connections["\\Q"]; - sig.optimize(); if (sig.chunks().size() == 1 && sig.chunks()[0].wire) for (int i = 0; i < sig.chunks()[0].width; i++) -- cgit v1.2.3 From 5826670009e1018734de49aaf1554cb8a43d09d7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 14:23:31 +0200 Subject: Various RTLIL::SigSpec related code cleanups --- backends/verilog/verilog_backend.cc | 50 +++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 21 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 1dcc3003a..a22035edb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -133,18 +133,23 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { - if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) + if (!sig.is_chunk() || sig.as_chunk().wire == NULL) return false; - if (reg_wires.count(sig.chunks()[0].wire->name) == 0) + + RTLIL::SigChunk chunk = sig.as_chunk(); + + if (reg_wires.count(chunk.wire->name) == 0) return false; - reg_name = id(sig.chunks()[0].wire->name); - if (sig.size() != sig.chunks()[0].wire->width) { + + reg_name = id(chunk.wire->name); + if (sig.size() != chunk.wire->width) { if (sig.size() == 1) - reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); + reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset); else - reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1, - sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); + reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1, + chunk.wire->start_offset + chunk.offset); } + return true; } @@ -220,8 +225,8 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) { - if (sig.chunks().size() == 1) { - dump_sigchunk(f, sig.chunks()[0]); + if (sig.is_chunk()) { + dump_sigchunk(f, sig.as_chunk()); } else { fprintf(f, "{ "); for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { @@ -299,10 +304,10 @@ std::string cellname(RTLIL::Cell *cell) if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0) { RTLIL::SigSpec sig = cell->connections["\\Q"]; - if (sig.size() != 1 || sig.is_fully_const()) + if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; - RTLIL::Wire *wire = sig.chunks()[0].wire; + RTLIL::Wire *wire = sig[0].wire; if (wire->name[0] != '\\') goto no_special_reg_name; @@ -316,7 +321,7 @@ std::string cellname(RTLIL::Cell *cell) cell_name = cell_name + "_reg"; if (wire->width != 1) - cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset); + cell_name += stringf("[%d]", wire->start_offset + sig[0].offset); if (active_module && active_module->count_id(cell_name) > 0) goto no_special_reg_name; @@ -809,9 +814,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs) case_body_find_regs(*it2); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - for (size_t i = 0; i < it->first.chunks().size(); i++) - if (it->first.chunks()[i].wire) - reg_wires.insert(it->first.chunks()[i].wire->name); + for (auto &c : it->first.chunks()) + if (c.wire != NULL) + reg_wires.insert(c.wire->name); } } @@ -821,9 +826,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r case_body_find_regs(&proc->root_case); for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++) for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) { - for (size_t i = 0; i < it2->first.chunks().size(); i++) - if (it2->first.chunks()[i].wire) - reg_wires.insert(it2->first.chunks()[i].wire->name); + for (auto &c : it2->first.chunks()) + if (c.wire != NULL) + reg_wires.insert(c.wire->name); } return; } @@ -908,9 +913,12 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) RTLIL::SigSpec sig = cell->connections["\\Q"]; - if (sig.chunks().size() == 1 && sig.chunks()[0].wire) - for (int i = 0; i < sig.chunks()[0].width; i++) - reg_bits.insert(std::pair(sig.chunks()[0].wire, sig.chunks()[0].offset+i)); + if (sig.is_chunk()) { + RTLIL::SigChunk chunk = sig.as_chunk(); + if (chunk.wire != NULL) + for (int i = 0; i < chunk.width; i++) + reg_bits.insert(std::pair(chunk.wire, chunk.offset+i)); + } } for (auto &it : module->wires) { -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- backends/verilog/verilog_backend.cc | 86 ++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 43 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a22035edb..d3b5d52db 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,17 +293,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections["\\" + port]); + dump_sigspec(f, cell->connections_["\\" + port]); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections["\\" + port]); + dump_sigspec(f, cell->connections_["\\" + port]); } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections_.count("\\Q") > 0) { - RTLIL::SigSpec sig = cell->connections["\\Q"]; + RTLIL::SigSpec sig = cell->connections_["\\Q"]; if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -338,7 +338,7 @@ no_special_reg_name: void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -348,7 +348,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", true); fprintf(f, " %s ", op.c_str()); @@ -361,7 +361,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_INV_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = "); fprintf(f, "~"); dump_attributes(f, "", cell->attributes, ' '); @@ -372,7 +372,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); @@ -391,7 +391,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = "); dump_cell_expr_port(f, cell, "S", false); fprintf(f, " ? "); @@ -406,23 +406,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections["\\C"]); + dump_sigspec(f, cell->connections_["\\C"]); if (cell->type[7] != '_') { fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections["\\R"]); + dump_sigspec(f, cell->connections_["\\R"]); } fprintf(f, ")\n"); if (cell->type[7] != '_') { fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections["\\R"]); + dump_sigspec(f, cell->connections_["\\R"]); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); fprintf(f, "%s" " else\n", indent.c_str()); @@ -434,7 +434,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Q"]); + dump_sigspec(f, cell->connections_["\\Q"]); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -446,27 +446,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections["\\C"]); + dump_sigspec(f, cell->connections_["\\C"]); fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections["\\S"]); + dump_sigspec(f, cell->connections_["\\S"]); fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections["\\R"]); + dump_sigspec(f, cell->connections_["\\R"]); fprintf(f, ")\n"); fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections["\\R"]); + dump_sigspec(f, cell->connections_["\\R"]); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections["\\S"]); + dump_sigspec(f, cell->connections_["\\S"]); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -477,7 +477,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Q"]); + dump_sigspec(f, cell->connections_["\\Q"]); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -535,7 +535,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections["\\S"].size(); + int s_width = cell->connections_["\\S"].size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -567,13 +567,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" "endfunction\n", indent.c_str()); fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = %s(", func_name.c_str()); - dump_sigspec(f, cell->connections["\\A"]); + dump_sigspec(f, cell->connections_["\\A"]); fprintf(f, ", "); - dump_sigspec(f, cell->connections["\\B"]); + dump_sigspec(f, cell->connections_["\\B"]); fprintf(f, ", "); - dump_sigspec(f, cell->connections["\\S"]); + dump_sigspec(f, cell->connections_["\\S"]); fprintf(f, ");\n"); return true; } @@ -581,9 +581,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = "); - dump_sigspec(f, cell->connections["\\A"]); + dump_sigspec(f, cell->connections_["\\A"]); fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -591,14 +591,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$bu0") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); if (cell->parameters["\\A_SIGNED"].as_bool()) { fprintf(f, " = $signed("); - dump_sigspec(f, cell->connections["\\A"]); + dump_sigspec(f, cell->connections_["\\A"]); fprintf(f, ");\n"); } else { fprintf(f, " = { 1'b0, "); - dump_sigspec(f, cell->connections["\\A"]); + dump_sigspec(f, cell->connections_["\\A"]); fprintf(f, " };\n"); } return true; @@ -607,11 +607,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Y"]); + dump_sigspec(f, cell->connections_["\\Y"]); fprintf(f, " = { "); - dump_sigspec(f, cell->connections["\\B"]); + dump_sigspec(f, cell->connections_["\\B"]); fprintf(f, " , "); - dump_sigspec(f, cell->connections["\\A"]); + dump_sigspec(f, cell->connections_["\\A"]); fprintf(f, " };\n"); return true; } @@ -621,17 +621,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk, sig_arst, val_arst; bool pol_clk, pol_arst = false; - sig_clk = cell->connections["\\CLK"]; + sig_clk = cell->connections_["\\CLK"]; pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - sig_arst = cell->connections["\\ARST"]; + sig_arst = cell->connections_["\\ARST"]; pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); @@ -660,7 +660,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections["\\Q"]); + dump_sigspec(f, cell->connections_["\\Q"]); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -707,7 +707,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); - for (auto it = cell->connections.begin(); it != cell->connections.end(); it++) { + for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { if (it->first != str) continue; if (!first_arg) @@ -721,7 +721,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) break; found_numbered_port:; } - for (auto it = cell->connections.begin(); it != cell->connections.end(); it++) { + for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { if (numbered_ports.count(it->first)) continue; if (!first_arg) @@ -908,10 +908,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections.count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || cell->connections_.count("\\Q") == 0) continue; - RTLIL::SigSpec sig = cell->connections["\\Q"]; + RTLIL::SigSpec sig = cell->connections_["\\Q"]; if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); @@ -961,7 +961,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second); - for (auto it = module->connections.begin(); it != module->connections.end(); it++) + for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) dump_conn(f, indent + " ", it->first, it->second); fprintf(f, "%s" "endmodule\n", indent.c_str()); -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- backends/verilog/verilog_backend.cc | 86 ++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 43 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d3b5d52db..aa2f88fa4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,17 +293,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections_.count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) { - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -338,7 +338,7 @@ no_special_reg_name: void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -348,7 +348,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", true); fprintf(f, " %s ", op.c_str()); @@ -361,7 +361,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_INV_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); fprintf(f, "~"); dump_attributes(f, "", cell->attributes, ' '); @@ -372,7 +372,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); @@ -391,7 +391,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "S", false); fprintf(f, " ? "); @@ -406,23 +406,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); if (cell->type[7] != '_') { fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); } fprintf(f, ")\n"); if (cell->type[7] != '_') { fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); fprintf(f, "%s" " else\n", indent.c_str()); @@ -434,7 +434,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -446,27 +446,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -477,7 +477,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -535,7 +535,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections_["\\S"].size(); + int s_width = cell->get("\\S").size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -567,13 +567,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" "endfunction\n", indent.c_str()); fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s(", func_name.c_str()); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ");\n"); return true; } @@ -581,9 +581,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -591,14 +591,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$bu0") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); if (cell->parameters["\\A_SIGNED"].as_bool()) { fprintf(f, " = $signed("); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ");\n"); } else { fprintf(f, " = { 1'b0, "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); } return true; @@ -607,11 +607,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = { "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, " , "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); return true; } @@ -621,17 +621,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk, sig_arst, val_arst; bool pol_clk, pol_arst = false; - sig_clk = cell->connections_["\\CLK"]; + sig_clk = cell->get("\\CLK"); pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - sig_arst = cell->connections_["\\ARST"]; + sig_arst = cell->get("\\ARST"); pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); @@ -660,7 +660,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -707,7 +707,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (it->first != str) continue; if (!first_arg) @@ -721,7 +721,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) break; found_numbered_port:; } - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (numbered_ports.count(it->first)) continue; if (!first_arg) @@ -908,10 +908,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections_.count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) continue; - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); @@ -961,7 +961,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second); - for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) + for (auto it = module->connections().begin(); it != module->connections().end(); it++) dump_conn(f, indent + " ", it->first, it->second); fprintf(f, "%s" "endmodule\n", indent.c_str()); -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- backends/verilog/verilog_backend.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index aa2f88fa4..6bef90e38 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals } } -void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) +void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig) { if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); @@ -293,10 +293,10 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections()["\\" + port]); + dump_sigspec(f, cell->get("\\" + port)); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections()["\\" + port]); + dump_sigspec(f, cell->get("\\" + port)); } std::string cellname(RTLIL::Cell *cell) @@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "\n%s" ");\n", indent.c_str()); } -void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right) +void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, left); -- cgit v1.2.3 From 97a59851a6c411ccb06162d4b31725bf89262378 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:11:28 +0200 Subject: Added RTLIL::Cell::has(portname) --- backends/verilog/verilog_backend.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6bef90e38..d9186c043 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -301,7 +301,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q")) { RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) @@ -908,7 +908,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q")) continue; RTLIL::SigSpec sig = cell->get("\\Q"); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/verilog/verilog_backend.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d9186c043..5e98a4c54 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -76,7 +76,7 @@ void reset_auto_counter(RTLIL::Module *module) reset_auto_counter_id(module->name, false); - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) reset_auto_counter_id(it->second->name, true); for (auto it = module->cells.begin(); it != module->cells.end(); it++) { @@ -920,7 +920,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) reg_bits.insert(std::pair(chunk.wire, chunk.offset+i)); } } - for (auto &it : module->wires) + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) @@ -936,7 +936,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { keep_running = false; - for (auto it = module->wires.begin(); it != module->wires.end(); it++) { + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) { RTLIL::Wire *wire = it->second; if (wire->port_id == port_id) { if (port_id != 1) @@ -949,7 +949,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) } fprintf(f, ");\n"); - for (auto it = module->wires.begin(); it != module->wires.end(); it++) + for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) dump_wire(f, indent + " ", it->second); for (auto it = module->memories.begin(); it != module->memories.end(); it++) -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- backends/verilog/verilog_backend.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 5e98a4c54..098e29f92 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -79,7 +79,7 @@ void reset_auto_counter(RTLIL::Module *module) for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) reset_auto_counter_id(it->second->name, true); - for (auto it = module->cells.begin(); it != module->cells.end(); it++) { + for (auto it = module->cells_.begin(); it != module->cells_.end(); it++) { reset_auto_counter_id(it->second->name, true); reset_auto_counter_id(it->second->type, false); } @@ -905,7 +905,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) if (!noexpr) { std::set> reg_bits; - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q")) @@ -955,7 +955,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->memories.begin(); it != module->memories.end(); it++) dump_memory(f, indent + " ", it->second); - for (auto it = module->cells.begin(); it != module->cells.end(); it++) + for (auto it = module->cells_.begin(); it != module->cells_.end(); it++) dump_cell(f, indent + " ", it->second); for (auto it = module->processes.begin(); it != module->processes.end(); it++) -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 098e29f92..f7f0ecaf4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1055,7 +1055,7 @@ struct VerilogBackend : public Backend { extra_args(f, filename, args, argidx); fprintf(f, "/* Generated by %s */\n", yosys_version_str); - for (auto it = design->modules.begin(); it != design->modules.end(); it++) { + for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) { if (it->second->get_bool_attribute("\\blackbox") != blackboxes) continue; if (selected && !design->selected_whole_module(it->first)) { -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- backends/verilog/verilog_backend.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index f7f0ecaf4..fe2c2b247 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -30,7 +30,6 @@ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/log.h" -#include #include #include #include @@ -161,7 +160,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = if (width == 32 && !no_decimal) { int32_t val = 0; for (int i = offset+width-1; i >= offset; i--) { - assert(i < (int)data.bits.size()); + log_assert(i < (int)data.bits.size()); if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) goto dump_bits; if (data.bits[i] == RTLIL::S1) @@ -175,7 +174,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = if (width == 0) fprintf(f, "0"); for (int i = offset+width-1; i >= offset; i--) { - assert(i < (int)data.bits.size()); + log_assert(i < (int)data.bits.size()); switch (data.bits[i]) { case RTLIL::S0: fprintf(f, "0"); break; case RTLIL::S1: fprintf(f, "1"); break; -- cgit v1.2.3 From 27a872d1e7041be4894bc643a420587ff5894125 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 14:25:03 +0200 Subject: Added support for "upto" wires to Verilog front- and back-end --- backends/verilog/verilog_backend.cc | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index fe2c2b247..5826aea87 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -211,14 +211,23 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal); } else { - if (chunk.width == chunk.wire->width && chunk.offset == 0) + if (chunk.width == chunk.wire->width && chunk.offset == 0) { fprintf(f, "%s", id(chunk.wire->name).c_str()); - else if (chunk.width == 1) - fprintf(f, "%s[%d]", id(chunk.wire->name).c_str(), chunk.offset + chunk.wire->start_offset); - else - fprintf(f, "%s[%d:%d]", id(chunk.wire->name).c_str(), - chunk.offset + chunk.wire->start_offset + chunk.width - 1, - chunk.offset + chunk.wire->start_offset); + } else if (chunk.width == 1) { + if (chunk.wire->upto) + fprintf(f, "%s[%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + else + fprintf(f, "%s[%d]", id(chunk.wire->name).c_str(), chunk.offset + chunk.wire->start_offset); + } else { + if (chunk.wire->upto) + fprintf(f, "%s[%d:%d]", id(chunk.wire->name).c_str(), + (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, + (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + else + fprintf(f, "%s[%d:%d]", id(chunk.wire->name).c_str(), + (chunk.offset + chunk.width - 1) + chunk.wire->start_offset, + chunk.offset + chunk.wire->start_offset); + } } } @@ -267,8 +276,12 @@ void dump_wire(FILE *f, std::string indent, RTLIL::Wire *wire) #else // do not use Verilog-2k "outut reg" syntax in verilog export std::string range = ""; - if (wire->width != 1) - range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset); + if (wire->width != 1) { + if (wire->upto) + range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset); + else + range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset); + } if (wire->port_input && !wire->port_output) fprintf(f, "%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); if (!wire->port_input && wire->port_output) -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- backends/verilog/verilog_backend.cc | 80 ++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 40 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 5826aea87..4bba32a63 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -305,17 +305,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->get("\\" + port)); + dump_sigspec(f, cell->getPort("\\" + port)); fprintf(f, ")"); } else - dump_sigspec(f, cell->get("\\" + port)); + dump_sigspec(f, cell->getPort("\\" + port)); } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q")) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->hasPort("\\Q")) { - RTLIL::SigSpec sig = cell->get("\\Q"); + RTLIL::SigSpec sig = cell->getPort("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -350,7 +350,7 @@ no_special_reg_name: void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -360,7 +360,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", true); fprintf(f, " %s ", op.c_str()); @@ -373,7 +373,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_INV_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); fprintf(f, "~"); dump_attributes(f, "", cell->attributes, ' '); @@ -384,7 +384,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); @@ -403,7 +403,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "S", false); fprintf(f, " ? "); @@ -418,23 +418,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->get("\\C")); + dump_sigspec(f, cell->getPort("\\C")); if (cell->type[7] != '_') { fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->get("\\R")); + dump_sigspec(f, cell->getPort("\\R")); } fprintf(f, ")\n"); if (cell->type[7] != '_') { fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->get("\\R")); + dump_sigspec(f, cell->getPort("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); fprintf(f, "%s" " else\n", indent.c_str()); @@ -446,7 +446,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Q")); + dump_sigspec(f, cell->getPort("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -458,27 +458,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->get("\\C")); + dump_sigspec(f, cell->getPort("\\C")); fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->get("\\S")); + dump_sigspec(f, cell->getPort("\\S")); fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->get("\\R")); + dump_sigspec(f, cell->getPort("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->get("\\R")); + dump_sigspec(f, cell->getPort("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->get("\\S")); + dump_sigspec(f, cell->getPort("\\S")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -489,7 +489,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Q")); + dump_sigspec(f, cell->getPort("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -547,7 +547,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->get("\\S").size(); + int s_width = cell->getPort("\\S").size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -579,13 +579,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" "endfunction\n", indent.c_str()); fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = %s(", func_name.c_str()); - dump_sigspec(f, cell->get("\\A")); + dump_sigspec(f, cell->getPort("\\A")); fprintf(f, ", "); - dump_sigspec(f, cell->get("\\B")); + dump_sigspec(f, cell->getPort("\\B")); fprintf(f, ", "); - dump_sigspec(f, cell->get("\\S")); + dump_sigspec(f, cell->getPort("\\S")); fprintf(f, ");\n"); return true; } @@ -593,9 +593,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); - dump_sigspec(f, cell->get("\\A")); + dump_sigspec(f, cell->getPort("\\A")); fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -603,14 +603,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$bu0") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); if (cell->parameters["\\A_SIGNED"].as_bool()) { fprintf(f, " = $signed("); - dump_sigspec(f, cell->get("\\A")); + dump_sigspec(f, cell->getPort("\\A")); fprintf(f, ");\n"); } else { fprintf(f, " = { 1'b0, "); - dump_sigspec(f, cell->get("\\A")); + dump_sigspec(f, cell->getPort("\\A")); fprintf(f, " };\n"); } return true; @@ -619,11 +619,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Y")); + dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = { "); - dump_sigspec(f, cell->get("\\B")); + dump_sigspec(f, cell->getPort("\\B")); fprintf(f, " , "); - dump_sigspec(f, cell->get("\\A")); + dump_sigspec(f, cell->getPort("\\A")); fprintf(f, " };\n"); return true; } @@ -633,17 +633,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk, sig_arst, val_arst; bool pol_clk, pol_arst = false; - sig_clk = cell->get("\\CLK"); + sig_clk = cell->getPort("\\CLK"); pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - sig_arst = cell->get("\\ARST"); + sig_arst = cell->getPort("\\ARST"); pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); @@ -672,7 +672,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->get("\\Q")); + dump_sigspec(f, cell->getPort("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -920,10 +920,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q")) + if (!reg_ct.cell_known(cell->type) || !cell->hasPort("\\Q")) continue; - RTLIL::SigSpec sig = cell->get("\\Q"); + RTLIL::SigSpec sig = cell->getPort("\\Q"); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- backends/verilog/verilog_backend.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 4bba32a63..e3c930c8b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -39,14 +39,14 @@ namespace { bool norename, noattr, attr2comment, noexpr; int auto_name_counter, auto_name_offset, auto_name_digits; -std::map auto_name_map; +std::map auto_name_map; -std::set reg_wires; +std::set reg_wires; CellTypes reg_ct; RTLIL::Module *active_module; -void reset_auto_counter_id(const std::string &id, bool may_rename) +void reset_auto_counter_id(RTLIL::IdString id, bool may_rename) { const char *str = id.c_str(); @@ -94,7 +94,7 @@ void reset_auto_counter(RTLIL::Module *module) log(" renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second); } -std::string id(std::string internal_id, bool may_rename = true) +std::string id(RTLIL::IdString internal_id, bool may_rename = true) { const char *str = internal_id.c_str(); bool do_escape = false; @@ -324,7 +324,7 @@ std::string cellname(RTLIL::Cell *cell) if (wire->name[0] != '\\') goto no_special_reg_name; - std::string cell_name = wire->name; + std::string cell_name = wire->name.str(); size_t pos = cell_name.find('['); if (pos != std::string::npos) @@ -715,7 +715,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, " %s (", cell_name.c_str()); bool first_arg = true; - std::set numbered_ports; + std::set numbered_ports; for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); -- cgit v1.2.3 From ca1b5d50e0e577a88ae265b71679b81e71980db8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 21:10:08 +0200 Subject: Improved verilog output for ordinary $mux cells --- backends/verilog/verilog_backend.cc | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e3c930c8b..c691eae60 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -544,7 +544,22 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) #undef HANDLE_UNIOP #undef HANDLE_BINOP - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") + if (cell->type == "$mux") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = "); + dump_sigspec(f, cell->getPort("\\S")); + fprintf(f, " ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_sigspec(f, cell->getPort("\\B")); + fprintf(f, " : "); + dump_sigspec(f, cell->getPort("\\A")); + fprintf(f, ";\n"); + return true; + } + + if (cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); int s_width = cell->getPort("\\S").size(); @@ -556,10 +571,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); dump_attributes(f, indent + " ", cell->attributes); - if (!noattr) + if (cell->type != "$pmux_safe" && !noattr) fprintf(f, "%s" " (* parallel_case *)\n", indent.c_str()); fprintf(f, "%s" " casez (s)", indent.c_str()); - fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); + if (cell->type != "$pmux_safe") + fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); for (int i = 0; i < s_width; i++) { -- cgit v1.2.3 From 88cf00ce7874ec7951b09d85e959dd2c6ed261b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 21:54:02 +0200 Subject: Be more conservative with printing decimal numbers in verilog backend --- backends/verilog/verilog_backend.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index c691eae60..605616b31 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -163,11 +163,12 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = log_assert(i < (int)data.bits.size()); if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) goto dump_bits; + if (data.bits[i] == RTLIL::S1 && (i - offset) == 31) + goto dump_bits; if (data.bits[i] == RTLIL::S1) val |= 1 << (i - offset); } - // fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val)); - fprintf(f, "%d", val); + fprintf(f, "32'%sd%d", set_signed ? "s" : "", val); } else { dump_bits: fprintf(f, "%d'%sb", width, set_signed ? "s" : ""); -- cgit v1.2.3 From 746aac540b815099c6a63077010555369d7fdd5a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 15:46:51 +0200 Subject: Refactoring of CellType class --- backends/verilog/verilog_backend.cc | 38 +++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 605616b31..cafc1f3f0 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -40,10 +40,8 @@ namespace { bool norename, noattr, attr2comment, noexpr; int auto_name_counter, auto_name_offset, auto_name_digits; std::map auto_name_map; +std::set reg_wires, reg_ct; -std::set reg_wires; - -CellTypes reg_ct; RTLIL::Module *active_module; void reset_auto_counter_id(RTLIL::IdString id, bool may_rename) @@ -314,7 +312,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->hasPort("\\Q")) + if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { RTLIL::SigSpec sig = cell->getPort("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) @@ -696,7 +694,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } - // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_ + // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_ // FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm return false; @@ -937,7 +935,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || !cell->hasPort("\\Q")) + if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q")) continue; RTLIL::SigSpec sig = cell->getPort("\\Q"); @@ -1047,10 +1045,30 @@ struct VerilogBackend : public Backend { bool selected = false; reg_ct.clear(); - reg_ct.setup_stdcells_mem(); - reg_ct.cell_types.insert("$sr"); - reg_ct.cell_types.insert("$dff"); - reg_ct.cell_types.insert("$adff"); + + reg_ct.insert("$dff"); + reg_ct.insert("$adff"); + + reg_ct.insert("$_DFF_N_"); + reg_ct.insert("$_DFF_P_"); + + reg_ct.insert("$_DFF_NN0_"); + reg_ct.insert("$_DFF_NN1_"); + reg_ct.insert("$_DFF_NP0_"); + reg_ct.insert("$_DFF_NP1_"); + reg_ct.insert("$_DFF_PN0_"); + reg_ct.insert("$_DFF_PN1_"); + reg_ct.insert("$_DFF_PP0_"); + reg_ct.insert("$_DFF_PP1_"); + + reg_ct.insert("$_DFFSR_NNN_"); + reg_ct.insert("$_DFFSR_NNP_"); + reg_ct.insert("$_DFFSR_NPN_"); + reg_ct.insert("$_DFFSR_NPP_"); + reg_ct.insert("$_DFFSR_PNN_"); + reg_ct.insert("$_DFFSR_PNP_"); + reg_ct.insert("$_DFFSR_PPN_"); + reg_ct.insert("$_DFFSR_PPP_"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { -- cgit v1.2.3 From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:11:40 +0200 Subject: Renamed $_INV_ cell type to $_NOT_ --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index cafc1f3f0..81c938bdd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -370,7 +370,7 @@ void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { - if (cell->type == "$_INV_") { + if (cell->type == "$_NOT_") { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); -- cgit v1.2.3 From 47c2637a961839f1eb1a0386f7e54d94be50bc10 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 18:18:30 +0200 Subject: Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ --- backends/verilog/verilog_backend.cc | 44 +++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 81c938bdd..0fcd60cdd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -381,21 +381,25 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); + if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) + fprintf(f, "~("); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); - if (cell->type == "$_AND_") + if (cell->type.in("$_AND_", "$_NAND_")) fprintf(f, "&"); - if (cell->type == "$_OR_") + if (cell->type.in("$_OR_", "$_NOR_")) fprintf(f, "|"); - if (cell->type == "$_XOR_") + if (cell->type.in("$_XOR_", "$_XNOR_")) fprintf(f, "^"); dump_attributes(f, "", cell->attributes, ' '); fprintf(f, " "); dump_cell_expr_port(f, cell, "B", false); + if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) + fprintf(f, ")"); fprintf(f, ";\n"); return true; } @@ -414,6 +418,38 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type.in("$_AOI3_", "$_OAI3_")) { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = ("); + dump_cell_expr_port(f, cell, "A", false); + fprintf(f, cell->type == "$_AOI3_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "B", false); + fprintf(f, cell->type == "$_AOI3_" ? ") |" : ") &"); + dump_attributes(f, "", cell->attributes, ' '); + fprintf(f, " "); + dump_cell_expr_port(f, cell, "C", false); + fprintf(f, ";\n"); + return true; + } + + if (cell->type.in("$_AOI4_", "$_OAI4_")) { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = ("); + dump_cell_expr_port(f, cell, "A", false); + fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "B", false); + fprintf(f, cell->type == "$_AOI4_" ? ") |" : ") &"); + dump_attributes(f, "", cell->attributes, ' '); + fprintf(f, " ("); + dump_cell_expr_port(f, cell, "C", false); + fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + dump_cell_expr_port(f, cell, "D", false); + fprintf(f, ");\n"); + return true; + } + if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); -- cgit v1.2.3 From f82c978e08604c596b034fb6e74ac34c78b9364b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 22:05:09 +0200 Subject: Fixed AOI/OAI expr handling in verilog backend --- backends/verilog/verilog_backend.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 0fcd60cdd..f6095a5aa 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -421,7 +421,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.in("$_AOI3_", "$_OAI3_")) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = ("); + fprintf(f, " = ~(("); dump_cell_expr_port(f, cell, "A", false); fprintf(f, cell->type == "$_AOI3_" ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); @@ -429,14 +429,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) dump_attributes(f, "", cell->attributes, ' '); fprintf(f, " "); dump_cell_expr_port(f, cell, "C", false); - fprintf(f, ";\n"); + fprintf(f, ");\n"); return true; } if (cell->type.in("$_AOI4_", "$_OAI4_")) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = ("); + fprintf(f, " = ~(("); dump_cell_expr_port(f, cell, "A", false); fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); @@ -446,7 +446,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) dump_cell_expr_port(f, cell, "C", false); fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); dump_cell_expr_port(f, cell, "D", false); - fprintf(f, ");\n"); + fprintf(f, "));\n"); return true; } -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- backends/verilog/verilog_backend.cc | 460 ++++++++++++++++++------------------ backends/verilog/verilog_backend.h | 5 +- 2 files changed, 232 insertions(+), 233 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index f6095a5aa..d1fa55b94 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -150,7 +150,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) return true; } -void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) +void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false) { if (width < 0) width = data.bits.size() - offset; @@ -166,112 +166,112 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = if (data.bits[i] == RTLIL::S1) val |= 1 << (i - offset); } - fprintf(f, "32'%sd%d", set_signed ? "s" : "", val); + f << stringf("32'%sd%d", set_signed ? "s" : "", val); } else { dump_bits: - fprintf(f, "%d'%sb", width, set_signed ? "s" : ""); + f << stringf("%d'%sb", width, set_signed ? "s" : ""); if (width == 0) - fprintf(f, "0"); + f << stringf("0"); for (int i = offset+width-1; i >= offset; i--) { log_assert(i < (int)data.bits.size()); switch (data.bits[i]) { - case RTLIL::S0: fprintf(f, "0"); break; - case RTLIL::S1: fprintf(f, "1"); break; - case RTLIL::Sx: fprintf(f, "x"); break; - case RTLIL::Sz: fprintf(f, "z"); break; - case RTLIL::Sa: fprintf(f, "z"); break; + case RTLIL::S0: f << stringf("0"); break; + case RTLIL::S1: f << stringf("1"); break; + case RTLIL::Sx: f << stringf("x"); break; + case RTLIL::Sz: f << stringf("z"); break; + case RTLIL::Sa: f << stringf("z"); break; case RTLIL::Sm: log_error("Found marker state in final netlist."); } } } } else { - fprintf(f, "\""); + f << stringf("\""); std::string str = data.decode_string(); for (size_t i = 0; i < str.size(); i++) { if (str[i] == '\n') - fprintf(f, "\\n"); + f << stringf("\\n"); else if (str[i] == '\t') - fprintf(f, "\\t"); + f << stringf("\\t"); else if (str[i] < 32) - fprintf(f, "\\%03o", str[i]); + f << stringf("\\%03o", str[i]); else if (str[i] == '"') - fprintf(f, "\\\""); + f << stringf("\\\""); else if (str[i] == '\\') - fprintf(f, "\\\\"); + f << stringf("\\\\"); else - fputc(str[i], f); + f << str[i]; } - fprintf(f, "\""); + f << stringf("\""); } } -void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false) +void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decimal = false) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal); } else { if (chunk.width == chunk.wire->width && chunk.offset == 0) { - fprintf(f, "%s", id(chunk.wire->name).c_str()); + f << stringf("%s", id(chunk.wire->name).c_str()); } else if (chunk.width == 1) { if (chunk.wire->upto) - fprintf(f, "%s[%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + f << stringf("%s[%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); else - fprintf(f, "%s[%d]", id(chunk.wire->name).c_str(), chunk.offset + chunk.wire->start_offset); + f << stringf("%s[%d]", id(chunk.wire->name).c_str(), chunk.offset + chunk.wire->start_offset); } else { if (chunk.wire->upto) - fprintf(f, "%s[%d:%d]", id(chunk.wire->name).c_str(), + f << stringf("%s[%d:%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); else - fprintf(f, "%s[%d:%d]", id(chunk.wire->name).c_str(), + f << stringf("%s[%d:%d]", id(chunk.wire->name).c_str(), (chunk.offset + chunk.width - 1) + chunk.wire->start_offset, chunk.offset + chunk.wire->start_offset); } } } -void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig) +void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) { if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); } else { - fprintf(f, "{ "); + f << stringf("{ "); for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { if (it != sig.chunks().rbegin()) - fprintf(f, ", "); + f << stringf(", "); dump_sigchunk(f, *it, true); } - fprintf(f, " }"); + f << stringf(" }"); } } -void dump_attributes(FILE *f, std::string indent, std::map &attributes, char term = '\n') +void dump_attributes(std::ostream &f, std::string indent, std::map &attributes, char term = '\n') { if (noattr) return; for (auto it = attributes.begin(); it != attributes.end(); it++) { - fprintf(f, "%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str()); - fprintf(f, " = "); + f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str()); + f << stringf(" = "); dump_const(f, it->second); - fprintf(f, " %s%c", attr2comment ? "*/" : "*)", term); + f << stringf(" %s%c", attr2comment ? "*/" : "*)", term); } } -void dump_wire(FILE *f, std::string indent, RTLIL::Wire *wire) +void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) { dump_attributes(f, indent, wire->attributes); #if 0 if (wire->port_input && !wire->port_output) - fprintf(f, "%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); else if (!wire->port_input && wire->port_output) - fprintf(f, "%s" "output %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "output %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); else if (wire->port_input && wire->port_output) - fprintf(f, "%s" "inout %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "inout %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); else - fprintf(f, "%s" "%s ", indent.c_str(), reg_wires.count(wire->name) ? "reg" : "wire"); + f << stringf("%s" "%s ", indent.c_str(), reg_wires.count(wire->name) ? "reg" : "wire"); if (wire->width != 1) - fprintf(f, "[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset); - fprintf(f, "%s;\n", id(wire->name).c_str()); + f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset); + f << stringf("%s;\n", id(wire->name).c_str()); #else // do not use Verilog-2k "outut reg" syntax in verilog export std::string range = ""; @@ -282,30 +282,30 @@ void dump_wire(FILE *f, std::string indent, RTLIL::Wire *wire) range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset); } if (wire->port_input && !wire->port_output) - fprintf(f, "%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); if (!wire->port_input && wire->port_output) - fprintf(f, "%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); if (wire->port_input && wire->port_output) - fprintf(f, "%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); if (reg_wires.count(wire->name)) - fprintf(f, "%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); else if (!wire->port_input && !wire->port_output) - fprintf(f, "%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); #endif } -void dump_memory(FILE *f, std::string indent, RTLIL::Memory *memory) +void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory) { dump_attributes(f, indent, memory->attributes); - fprintf(f, "%s" "reg [%d:0] %s [%d:0];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size-1); + f << stringf("%s" "reg [%d:0] %s [%d:0];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size-1); } -void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_signed = true) +void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true) { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { - fprintf(f, "$signed("); + f << stringf("$signed("); dump_sigspec(f, cell->getPort("\\" + port)); - fprintf(f, ")"); + f << stringf(")"); } else dump_sigspec(f, cell->getPort("\\" + port)); } @@ -346,107 +346,107 @@ no_special_reg_name: } } -void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) +void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = %s ", op.c_str()); + f << stringf(" = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); - fprintf(f, ";\n"); + f << stringf(";\n"); } -void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) +void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); + f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); - fprintf(f, " %s ", op.c_str()); + f << stringf(" %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "B", true); - fprintf(f, ";\n"); + f << stringf(";\n"); } -bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) +bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_NOT_") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); - fprintf(f, "~"); + f << stringf(" = "); + f << stringf("~"); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", false); - fprintf(f, ";\n"); + f << stringf(";\n"); return true; } if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); + f << stringf(" = "); if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) - fprintf(f, "~("); + f << stringf("~("); dump_cell_expr_port(f, cell, "A", false); - fprintf(f, " "); + f << stringf(" "); if (cell->type.in("$_AND_", "$_NAND_")) - fprintf(f, "&"); + f << stringf("&"); if (cell->type.in("$_OR_", "$_NOR_")) - fprintf(f, "|"); + f << stringf("|"); if (cell->type.in("$_XOR_", "$_XNOR_")) - fprintf(f, "^"); + f << stringf("^"); dump_attributes(f, "", cell->attributes, ' '); - fprintf(f, " "); + f << stringf(" "); dump_cell_expr_port(f, cell, "B", false); if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) - fprintf(f, ")"); - fprintf(f, ";\n"); + f << stringf(")"); + f << stringf(";\n"); return true; } if (cell->type == "$_MUX_") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); + f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); - fprintf(f, " ? "); + f << stringf(" ? "); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "B", false); - fprintf(f, " : "); + f << stringf(" : "); dump_cell_expr_port(f, cell, "A", false); - fprintf(f, ";\n"); + f << stringf(";\n"); return true; } if (cell->type.in("$_AOI3_", "$_OAI3_")) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = ~(("); + f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - fprintf(f, cell->type == "$_AOI3_" ? " & " : " | "); + f << stringf(cell->type == "$_AOI3_" ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - fprintf(f, cell->type == "$_AOI3_" ? ") |" : ") &"); + f << stringf(cell->type == "$_AOI3_" ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, ' '); - fprintf(f, " "); + f << stringf(" "); dump_cell_expr_port(f, cell, "C", false); - fprintf(f, ");\n"); + f << stringf(");\n"); return true; } if (cell->type.in("$_AOI4_", "$_OAI4_")) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = ~(("); + f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); - fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); - fprintf(f, cell->type == "$_AOI4_" ? ") |" : ") &"); + f << stringf(cell->type == "$_AOI4_" ? ") |" : ") &"); dump_attributes(f, "", cell->attributes, ' '); - fprintf(f, " ("); + f << stringf(" ("); dump_cell_expr_port(f, cell, "C", false); - fprintf(f, cell->type == "$_AOI4_" ? " & " : " | "); + f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); dump_cell_expr_port(f, cell, "D", false); - fprintf(f, "));\n"); + f << stringf("));\n"); return true; } @@ -456,33 +456,33 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) - fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); + f << stringf("%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); - fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); + f << stringf("%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\C")); if (cell->type[7] != '_') { - fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); + f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\R")); } - fprintf(f, ")\n"); + f << stringf(")\n"); if (cell->type[7] != '_') { - fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); + f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); dump_sigspec(f, cell->getPort("\\R")); - fprintf(f, ")\n"); - fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); - fprintf(f, "%s" " else\n", indent.c_str()); + f << stringf(")\n"); + f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); + f << stringf("%s" " else\n", indent.c_str()); } - fprintf(f, "%s" " %s <= ", indent.c_str(), reg_name.c_str()); + f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str()); dump_cell_expr_port(f, cell, "D", false); - fprintf(f, ";\n"); + f << stringf(";\n"); if (!out_is_reg_wire) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Q")); - fprintf(f, " = %s;\n", reg_name.c_str()); + f << stringf(" = %s;\n", reg_name.c_str()); } return true; @@ -496,36 +496,36 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) - fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); + f << stringf("%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); - fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); + f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\C")); - fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); + f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\S")); - fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); + f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg"); dump_sigspec(f, cell->getPort("\\R")); - fprintf(f, ")\n"); + f << stringf(")\n"); - fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); + f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); dump_sigspec(f, cell->getPort("\\R")); - fprintf(f, ")\n"); - fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); + f << stringf(")\n"); + f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); - fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); + f << stringf("%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); dump_sigspec(f, cell->getPort("\\S")); - fprintf(f, ")\n"); - fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); + f << stringf(")\n"); + f << stringf("%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); - fprintf(f, "%s" " else\n", indent.c_str()); - fprintf(f, "%s" " %s <= ", indent.c_str(), reg_name.c_str()); + f << stringf("%s" " else\n", indent.c_str()); + f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str()); dump_cell_expr_port(f, cell, "D", false); - fprintf(f, ";\n"); + f << stringf(";\n"); if (!out_is_reg_wire) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Q")); - fprintf(f, " = %s;\n", reg_name.c_str()); + f << stringf(" = %s;\n", reg_name.c_str()); } return true; @@ -581,16 +581,16 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); + f << stringf(" = "); dump_sigspec(f, cell->getPort("\\S")); - fprintf(f, " ? "); + f << stringf(" ? "); dump_attributes(f, "", cell->attributes, ' '); dump_sigspec(f, cell->getPort("\\B")); - fprintf(f, " : "); + f << stringf(" : "); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, ";\n"); + f << stringf(";\n"); return true; } @@ -600,82 +600,82 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) int s_width = cell->getPort("\\S").size(); std::string func_name = cellname(cell); - fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); - fprintf(f, "%s" " input [%d:0] a;\n", indent.c_str(), width-1); - fprintf(f, "%s" " input [%d:0] b;\n", indent.c_str(), s_width*width-1); - fprintf(f, "%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); + f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); + f << stringf("%s" " input [%d:0] a;\n", indent.c_str(), width-1); + f << stringf("%s" " input [%d:0] b;\n", indent.c_str(), s_width*width-1); + f << stringf("%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); dump_attributes(f, indent + " ", cell->attributes); if (cell->type != "$pmux_safe" && !noattr) - fprintf(f, "%s" " (* parallel_case *)\n", indent.c_str()); - fprintf(f, "%s" " casez (s)", indent.c_str()); + f << stringf("%s" " (* parallel_case *)\n", indent.c_str()); + f << stringf("%s" " casez (s)", indent.c_str()); if (cell->type != "$pmux_safe") - fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); + f << stringf(noattr ? " // synopsys parallel_case\n" : "\n"); for (int i = 0; i < s_width; i++) { - fprintf(f, "%s" " %d'b", indent.c_str(), s_width); + f << stringf("%s" " %d'b", indent.c_str(), s_width); for (int j = s_width-1; j >= 0; j--) - fprintf(f, "%c", j == i ? '1' : cell->type == "$pmux_safe" ? '0' : '?'); + f << stringf("%c", j == i ? '1' : cell->type == "$pmux_safe" ? '0' : '?'); - fprintf(f, ":\n"); - fprintf(f, "%s" " %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width); + f << stringf(":\n"); + f << stringf("%s" " %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width); } - fprintf(f, "%s" " default:\n", indent.c_str()); - fprintf(f, "%s" " %s = a;\n", indent.c_str(), func_name.c_str()); + f << stringf("%s" " default:\n", indent.c_str()); + f << stringf("%s" " %s = a;\n", indent.c_str(), func_name.c_str()); - fprintf(f, "%s" " endcase\n", indent.c_str()); - fprintf(f, "%s" "endfunction\n", indent.c_str()); + f << stringf("%s" " endcase\n", indent.c_str()); + f << stringf("%s" "endfunction\n", indent.c_str()); - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = %s(", func_name.c_str()); + f << stringf(" = %s(", func_name.c_str()); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, ", "); + f << stringf(", "); dump_sigspec(f, cell->getPort("\\B")); - fprintf(f, ", "); + f << stringf(", "); dump_sigspec(f, cell->getPort("\\S")); - fprintf(f, ");\n"); + f << stringf(");\n"); return true; } if (cell->type == "$slice") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = "); + f << stringf(" = "); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); + f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } if (cell->type == "$bu0") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); if (cell->parameters["\\A_SIGNED"].as_bool()) { - fprintf(f, " = $signed("); + f << stringf(" = $signed("); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, ");\n"); + f << stringf(");\n"); } else { - fprintf(f, " = { 1'b0, "); + f << stringf(" = { 1'b0, "); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, " };\n"); + f << stringf(" };\n"); } return true; } if (cell->type == "$concat") { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); - fprintf(f, " = { "); + f << stringf(" = { "); dump_sigspec(f, cell->getPort("\\B")); - fprintf(f, " , "); + f << stringf(" , "); dump_sigspec(f, cell->getPort("\\A")); - fprintf(f, " };\n"); + f << stringf(" };\n"); return true; } @@ -697,34 +697,34 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); if (!out_is_reg_wire) - fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); + f << stringf("%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); - fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg"); + f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg"); dump_sigspec(f, sig_clk); if (cell->type == "$adff") { - fprintf(f, " or %sedge ", pol_arst ? "pos" : "neg"); + f << stringf(" or %sedge ", pol_arst ? "pos" : "neg"); dump_sigspec(f, sig_arst); } - fprintf(f, ")\n"); + f << stringf(")\n"); if (cell->type == "$adff") { - fprintf(f, "%s" " if (%s", indent.c_str(), pol_arst ? "" : "!"); + f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!"); dump_sigspec(f, sig_arst); - fprintf(f, ")\n"); - fprintf(f, "%s" " %s <= ", indent.c_str(), reg_name.c_str()); + f << stringf(")\n"); + f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str()); dump_sigspec(f, val_arst); - fprintf(f, ";\n"); - fprintf(f, "%s" " else\n", indent.c_str()); + f << stringf(";\n"); + f << stringf("%s" " else\n", indent.c_str()); } - fprintf(f, "%s" " %s <= ", indent.c_str(), reg_name.c_str()); + f << stringf("%s" " %s <= ", indent.c_str(), reg_name.c_str()); dump_cell_expr_port(f, cell, "D", false); - fprintf(f, ";\n"); + f << stringf(";\n"); if (!out_is_reg_wire) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Q")); - fprintf(f, " = %s;\n", reg_name.c_str()); + f << stringf(" = %s;\n", reg_name.c_str()); } return true; @@ -736,7 +736,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return false; } -void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) +void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type[0] == '$' && !noexpr) { if (dump_cell_expr(f, indent, cell)) @@ -744,26 +744,26 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) } dump_attributes(f, indent, cell->attributes); - fprintf(f, "%s" "%s", indent.c_str(), id(cell->type, false).c_str()); + f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); if (cell->parameters.size() > 0) { - fprintf(f, " #("); + f << stringf(" #("); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); it++) { if (it != cell->parameters.begin()) - fprintf(f, ","); - fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); + f << stringf(","); + f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0; dump_const(f, it->second, -1, 0, !is_signed, is_signed); - fprintf(f, ")"); + f << stringf(")"); } - fprintf(f, "\n%s" ")", indent.c_str()); + f << stringf("\n%s" ")", indent.c_str()); } std::string cell_name = cellname(cell); if (cell_name != id(cell->name)) - fprintf(f, " %s /* %s */ (", cell_name.c_str(), id(cell->name).c_str()); + f << stringf(" %s /* %s */ (", cell_name.c_str(), id(cell->name).c_str()); else - fprintf(f, " %s (", cell_name.c_str()); + f << stringf(" %s (", cell_name.c_str()); bool first_arg = true; std::set numbered_ports; @@ -774,9 +774,9 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) if (it->first != str) continue; if (!first_arg) - fprintf(f, ","); + f << stringf(","); first_arg = false; - fprintf(f, "\n%s ", indent.c_str()); + f << stringf("\n%s ", indent.c_str()); dump_sigspec(f, it->second); numbered_ports.insert(it->first); goto found_numbered_port; @@ -788,86 +788,86 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) if (numbered_ports.count(it->first)) continue; if (!first_arg) - fprintf(f, ","); + f << stringf(","); first_arg = false; - fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); + f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); if (it->second.size() > 0) dump_sigspec(f, it->second); - fprintf(f, ")"); + f << stringf(")"); } - fprintf(f, "\n%s" ");\n", indent.c_str()); + f << stringf("\n%s" ");\n", indent.c_str()); } -void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) +void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { - fprintf(f, "%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, left); - fprintf(f, " = "); + f << stringf(" = "); dump_sigspec(f, right); - fprintf(f, ";\n"); + f << stringf(";\n"); } -void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw); +void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw); -void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false) +void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false) { int number_of_stmts = cs->switches.size() + cs->actions.size(); if (!omit_trailing_begin && number_of_stmts >= 2) - fprintf(f, "%s" "begin\n", indent.c_str()); + f << stringf("%s" "begin\n", indent.c_str()); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { if (it->first.size() == 0) continue; - fprintf(f, "%s ", indent.c_str()); + f << stringf("%s ", indent.c_str()); dump_sigspec(f, it->first); - fprintf(f, " = "); + f << stringf(" = "); dump_sigspec(f, it->second); - fprintf(f, ";\n"); + f << stringf(";\n"); } for (auto it = cs->switches.begin(); it != cs->switches.end(); it++) dump_proc_switch(f, indent + " ", *it); if (!omit_trailing_begin && number_of_stmts == 0) - fprintf(f, "%s /* empty */;\n", indent.c_str()); + f << stringf("%s /* empty */;\n", indent.c_str()); if (omit_trailing_begin || number_of_stmts >= 2) - fprintf(f, "%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent.c_str()); } -void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw) +void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) { if (sw->signal.size() == 0) { - fprintf(f, "%s" "begin\n", indent.c_str()); + f << stringf("%s" "begin\n", indent.c_str()); for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) { if ((*it)->compare.size() == 0) dump_case_body(f, indent + " ", *it); } - fprintf(f, "%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent.c_str()); return; } - fprintf(f, "%s" "casez (", indent.c_str()); + f << stringf("%s" "casez (", indent.c_str()); dump_sigspec(f, sw->signal); - fprintf(f, ")\n"); + f << stringf(")\n"); for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) { - fprintf(f, "%s ", indent.c_str()); + f << stringf("%s ", indent.c_str()); if ((*it)->compare.size() == 0) - fprintf(f, "default"); + f << stringf("default"); else { for (size_t i = 0; i < (*it)->compare.size(); i++) { if (i > 0) - fprintf(f, ", "); + f << stringf(", "); dump_sigspec(f, (*it)->compare[i]); } } - fprintf(f, ":\n"); + f << stringf(":\n"); dump_case_body(f, indent + " ", *it); } - fprintf(f, "%s" "endcase\n", indent.c_str()); + f << stringf("%s" "endcase\n", indent.c_str()); } void case_body_find_regs(RTLIL::CaseRule *cs) @@ -883,7 +883,7 @@ void case_body_find_regs(RTLIL::CaseRule *cs) } } -void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_regs = false) +void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, bool find_regs = false) { if (find_regs) { case_body_find_regs(&proc->root_case); @@ -896,7 +896,7 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r return; } - fprintf(f, "%s" "always @* begin\n", indent.c_str()); + f << stringf("%s" "always @* begin\n", indent.c_str()); dump_case_body(f, indent, &proc->root_case, true); std::string backup_indent = indent; @@ -907,23 +907,23 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r indent = backup_indent; if (sync->type == RTLIL::STa) { - fprintf(f, "%s" "always @* begin\n", indent.c_str()); + f << stringf("%s" "always @* begin\n", indent.c_str()); } else { - fprintf(f, "%s" "always @(", indent.c_str()); + f << stringf("%s" "always @(", indent.c_str()); if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1) - fprintf(f, "posedge "); + f << stringf("posedge "); if (sync->type == RTLIL::STn || sync->type == RTLIL::ST0) - fprintf(f, "negedge "); + f << stringf("negedge "); dump_sigspec(f, sync->signal); - fprintf(f, ") begin\n"); + f << stringf(") begin\n"); } std::string ends = indent + "end\n"; indent += " "; if (sync->type == RTLIL::ST0 || sync->type == RTLIL::ST1) { - fprintf(f, "%s" "if (%s", indent.c_str(), sync->type == RTLIL::ST0 ? "!" : ""); + f << stringf("%s" "if (%s", indent.c_str(), sync->type == RTLIL::ST0 ? "!" : ""); dump_sigspec(f, sync->signal); - fprintf(f, ") begin\n"); + f << stringf(") begin\n"); ends = indent + "end\n" + ends; indent += " "; } @@ -932,9 +932,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r for (size_t j = 0; j < proc->syncs.size(); j++) { RTLIL::SyncRule *sync2 = proc->syncs[j]; if (sync2->type == RTLIL::ST0 || sync2->type == RTLIL::ST1) { - fprintf(f, "%s" "if (%s", indent.c_str(), sync2->type == RTLIL::ST1 ? "!" : ""); + f << stringf("%s" "if (%s", indent.c_str(), sync2->type == RTLIL::ST1 ? "!" : ""); dump_sigspec(f, sync2->signal); - fprintf(f, ") begin\n"); + f << stringf(") begin\n"); ends = indent + "end\n" + ends; indent += " "; } @@ -944,24 +944,24 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) { if (it->first.size() == 0) continue; - fprintf(f, "%s ", indent.c_str()); + f << stringf("%s ", indent.c_str()); dump_sigspec(f, it->first); - fprintf(f, " <= "); + f << stringf(" <= "); dump_sigspec(f, it->second); - fprintf(f, ";\n"); + f << stringf(";\n"); } - fprintf(f, "%s", ends.c_str()); + f << stringf("%s", ends.c_str()); } } -void dump_module(FILE *f, std::string indent, RTLIL::Module *module) +void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) { reg_wires.clear(); reset_auto_counter(module); active_module = module; - fprintf(f, "\n"); + f << stringf("\n"); for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second, true); @@ -995,7 +995,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) } dump_attributes(f, indent, module->attributes); - fprintf(f, "%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); + f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { keep_running = false; @@ -1003,14 +1003,14 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) RTLIL::Wire *wire = it->second; if (wire->port_id == port_id) { if (port_id != 1) - fprintf(f, ", "); - fprintf(f, "%s", id(wire->name).c_str()); + f << stringf(", "); + f << stringf("%s", id(wire->name).c_str()); keep_running = true; continue; } } } - fprintf(f, ");\n"); + f << stringf(");\n"); for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) dump_wire(f, indent + " ", it->second); @@ -1027,7 +1027,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->connections().begin(); it != module->connections().end(); it++) dump_conn(f, indent + " ", it->first, it->second); - fprintf(f, "%s" "endmodule\n", indent.c_str()); + f << stringf("%s" "endmodule\n", indent.c_str()); active_module = NULL; } @@ -1068,7 +1068,7 @@ struct VerilogBackend : public Backend { log(" not at all.\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { log_header("Executing Verilog backend.\n"); @@ -1137,7 +1137,7 @@ struct VerilogBackend : public Backend { } extra_args(f, filename, args, argidx); - fprintf(f, "/* Generated by %s */\n", yosys_version_str); + *f << stringf("/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) { if (it->second->get_bool_attribute("\\blackbox") != blackboxes) continue; @@ -1147,7 +1147,7 @@ struct VerilogBackend : public Backend { continue; } log("Dumping module `%s'.\n", it->first.c_str()); - dump_module(f, "", it->second); + dump_module(*f, "", it->second); } reg_ct.clear(); diff --git a/backends/verilog/verilog_backend.h b/backends/verilog/verilog_backend.h index c40830ef2..7e6ef5ab9 100644 --- a/backends/verilog/verilog_backend.h +++ b/backends/verilog/verilog_backend.h @@ -29,11 +29,10 @@ #ifndef VERILOG_BACKEND_H #define VERILOG_BACKEND_H -#include "kernel/rtlil.h" -#include +#include "kernel/yosys.h" namespace VERILOG_BACKEND { - void verilog_backend(FILE *f, std::vector args, RTLIL::Design *design); + void verilog_backend(std::ostream &f, std::vector args, RTLIL::Design *design); } #endif -- cgit v1.2.3 From b9cb483f3e2a498ee75a422e09164a920918362b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 21:20:59 +0200 Subject: Using $pos models for $bu0 --- backends/verilog/verilog_backend.cc | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d1fa55b94..79672540b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) HANDLE_UNIOP("$not", "~") HANDLE_UNIOP("$pos", "+") + HANDLE_UNIOP("$bu0", "+") HANDLE_UNIOP("$neg", "-") HANDLE_BINOP("$and", "&") @@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type == "$bu0") - { - f << stringf("%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->getPort("\\Y")); - if (cell->parameters["\\A_SIGNED"].as_bool()) { - f << stringf(" = $signed("); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(");\n"); - } else { - f << stringf(" = { 1'b0, "); - dump_sigspec(f, cell->getPort("\\A")); - f << stringf(" };\n"); - } - return true; - } - if (cell->type == "$concat") { f << stringf("%s" "assign ", indent.c_str()); -- cgit v1.2.3 From 8927aa6148f5575b2da9bfb76afb4af076fe18f3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 4 Sep 2014 02:07:52 +0200 Subject: Removed $bu0 cell type --- backends/verilog/verilog_backend.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 79672540b..82a2c519e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -538,7 +538,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) HANDLE_UNIOP("$not", "~") HANDLE_UNIOP("$pos", "+") - HANDLE_UNIOP("$bu0", "+") HANDLE_UNIOP("$neg", "-") HANDLE_BINOP("$and", "&") -- cgit v1.2.3 From 9329a768181d3765a08c3b264c8b0031b732c0d4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 20:30:46 +0200 Subject: Various bug fixes (related to $macc model testing) --- backends/verilog/verilog_backend.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 82a2c519e..bbdbbbfaf 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) for (int i = 0; i < wire->width; i++) if (reg_bits.count(std::pair(wire, i)) == 0) goto this_wire_aint_reg; - reg_wires.insert(wire->name); + if (wire->width) + reg_wires.insert(wire->name); this_wire_aint_reg:; } } -- cgit v1.2.3