From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 backends/verilog/verilog_backend.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index b50dc12af..44e4e5f97 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1482,7 +1482,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 
 struct VerilogBackend : public Backend {
 	VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1550,7 +1550,7 @@ struct VerilogBackend : public Backend {
 		log("this command is called on a design with RTLIL processes.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing Verilog backend.\n");
 
-- 
cgit v1.2.3


From 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Sep 2018 00:18:01 +0200
Subject: Add $lut support to Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 44e4e5f97..d3262ec47 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$lut")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_const(f, cell->parameters.at("\\LUT"));
+		f << stringf(" >> ");
+		dump_attributes(f, "", cell->attributes, ' ');
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+		return true;
+	}
+
 	if (cell->type == "$dffsr")
 	{
 		SigSpec sig_clk = cell->getPort("\\CLK");
-- 
cgit v1.2.3


From efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Tue, 18 Sep 2018 13:34:30 -0400
Subject: Fixed typo in "verilog_write" help message

---
 backends/verilog/verilog_backend.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d3262ec47..ae9031510 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1523,7 +1523,7 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nodec\n");
 		log("        32-bit constant values are by default dumped as decimal numbers,\n");
-		log("        not bit pattern. This option decativates this feature and instead\n");
+		log("        not bit pattern. This option deactivates this feature and instead\n");
 		log("        will write out all constants in binary.\n");
 		log("\n");
 		log("    -decimal\n");
@@ -1531,13 +1531,13 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nohex\n");
 		log("        constant values that are compatible with hex output are usually\n");
-		log("        dumped as hex values. This option decativates this feature and\n");
+		log("        dumped as hex values. This option deactivates this feature and\n");
 		log("        instead will write out all constants in binary.\n");
 		log("\n");
 		log("    -nostr\n");
 		log("        Parameters and attributes that are specified as strings in the\n");
 		log("        original input will be output as strings by this back-end. This\n");
-		log("        decativates this feature and instead will write string constants\n");
+		log("        deactivates this feature and instead will write string constants\n");
 		log("        as binary numbers.\n");
 		log("\n");
 		log("    -defparam\n");
-- 
cgit v1.2.3


From 609f46eeb7b23fec2140dcfaaa5f3a8377153f43 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Thu, 18 Oct 2018 16:20:21 -0700
Subject: adding offset info to memories

---
 backends/verilog/verilog_backend.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ae9031510..39683922f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -388,7 +388,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory)
 {
 	dump_attributes(f, indent, memory->attributes);
-	f << stringf("%s" "reg [%d:0] %s [%d:0];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size-1);
+	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), (memory->width-1), id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
 }
 
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true)
@@ -952,6 +952,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
 		int abits = cell->parameters["\\ABITS"].as_int();
 		int size = cell->parameters["\\SIZE"].as_int();
+		int offset = cell->parameters["\\OFFSET"].as_int();
 		int width = cell->parameters["\\WIDTH"].as_int();
 		bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef());
 
@@ -960,7 +961,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		//  initial begin
 		//    memid[0] = ...
 		//  end
-		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0);
+		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
 		if (use_init)
 		{
 			f << stringf("%s" "initial begin\n", indent.c_str());
-- 
cgit v1.2.3


From c7770d9eeaf9fba0c9d07e7cce020fe89ec71600 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Thu, 18 Oct 2018 16:22:33 -0700
Subject: adding offset info to memories

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 39683922f..dde03f920 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -388,7 +388,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory)
 {
 	dump_attributes(f, indent, memory->attributes);
-	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), (memory->width-1), id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
+	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
 }
 
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true)
-- 
cgit v1.2.3


From 7fe770a441a129c509fd4da04b60ada942a28bc8 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 18:48:06 +0000
Subject: write_verilog: correctly map RTLIL `sync init`.

---
 backends/verilog/verilog_backend.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..922b4c44c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
 		if (sync->type == RTLIL::STa) {
 			f << stringf("%s" "always @* begin\n", indent.c_str());
+		} else if (sync->type == RTLIL::STi) {
+			f << stringf("%s" "initial begin\n", indent.c_str());
 		} else {
 			f << stringf("%s" "always @(", indent.c_str());
 			if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)
-- 
cgit v1.2.3


From fccaa25ec1b053259a377991d8deba0f71021956 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 13 Dec 2018 04:36:02 +0000
Subject: write_verilog: add a missing newline.

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..850abfad7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
-				"processes to logic networks and registers.", log_id(module));
+				"processes to logic networks and registers.\n", log_id(module));
 
 	f << stringf("\n");
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
-- 
cgit v1.2.3


From ca866d384e666f27e2cd7bb80950d0a1dd7c0ebd Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 18:46:32 +0000
Subject: write_verilog: handle the $shift cell.

The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
---
 backends/verilog/verilog_backend.cc | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 3a47b478f..71db25f98 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -678,6 +678,35 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 #undef HANDLE_UNIOP
 #undef HANDLE_BINOP
 
+	if (cell->type == "$shift")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		if (cell->getParam("\\B_SIGNED").as_bool())
+		{
+			f << stringf("$signed(");
+			dump_sigspec(f, cell->getPort("\\B"));
+			f << stringf(")");
+			f << stringf(" < 0 ? ");
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" << - ");
+			dump_sigspec(f, cell->getPort("\\B"));
+			f << stringf(" : ");
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" >> ");
+			dump_sigspec(f, cell->getPort("\\B"));
+		}
+		else
+		{
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" >> ");
+			dump_sigspec(f, cell->getPort("\\B"));
+		}
+		f << stringf(";\n");
+		return true;
+	}
+
 	if (cell->type == "$shiftx")
 	{
 		f << stringf("%s" "assign ", indent.c_str());
-- 
cgit v1.2.3


From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 19:14:07 +0000
Subject: Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 71db25f98..2537e18e5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1447,7 +1447,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 
 	if (!module->processes.empty())
-		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
+		log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
 				"processes to logic networks and registers.\n", log_id(module));
-- 
cgit v1.2.3


From 6c5049f016538e887476bb66d3f653155fa354ff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 15 Jan 2019 10:55:27 +0100
Subject: Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 2537e18e5..8da3c0627 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$shiftx")
 	{
+		std::string temp_id = next_auto_id();
+		f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort("\\Y"));
-		f << stringf(" = ");
-		dump_sigspec(f, cell->getPort("\\A"));
-		f << stringf("[");
+		f << stringf(" = %s[", temp_id.c_str());
 		if (cell->getParam("\\B_SIGNED").as_bool())
 			f << stringf("$signed(");
 		dump_sigspec(f, cell->getPort("\\B"));
-- 
cgit v1.2.3


From 42c47a83dab873290040367455c48f619d83e2a3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sat, 26 Jan 2019 23:55:46 +0000
Subject: write_verilog: escape names that match SystemVerilog keywords.

---
 backends/verilog/verilog_backend.cc | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627..fc38afbda 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -126,6 +126,33 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true)
 		break;
 	}
 
+	const pool<string> keywords = {
+		// IEEE 1800-2017 Annex B
+		"accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before",
+		"begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle",
+		"checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint",
+		"cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker",
+		"endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage",
+		"endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually",
+		"expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function",
+		"generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies",
+		"import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface",
+		"intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint",
+		"macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor",
+		"noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive",
+		"priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent",
+		"pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat",
+		"restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until",
+		"s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify",
+		"specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on",
+		"sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1",
+		"tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with",
+		"untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while",
+		"wildcard", "wire", "with", "within", "wor", "xnor", "xor",
+	};
+	if (keywords.count(str))
+		do_escape = true;
+
 	if (do_escape)
 		return "\\" + std::string(str) + " ";
 	return std::string(str);
-- 
cgit v1.2.3


From 3d7925ad9f7840d5269b84d053ae808f36ccf762 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 27 Jan 2019 00:21:31 +0000
Subject: write_verilog: write $tribuf cell as ternary.

---
 backends/verilog/verilog_backend.cc | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627..54281e32e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -789,6 +789,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$tribuf")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(" ? ");
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
+		return true;
+	}
+
 	if (cell->type == "$slice")
 	{
 		f << stringf("%s" "assign ", indent.c_str());
-- 
cgit v1.2.3


From da65e1e8d9552f64e1e03c08108ca0532719bbfe Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 29 Jan 2019 02:24:00 +0000
Subject: write_verilog: correctly emit asynchronous transparent ports.

This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.
---
 backends/verilog/verilog_backend.cc | 79 +++++++++++++++++++------------------
 1 file changed, 41 insertions(+), 38 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a7f329ef8..60668f1f0 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1065,43 +1065,46 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
 			rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
 			rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
+			if (use_rd_clk)
 			{
-				std::ostringstream os;
-				dump_sigspec(os, sig_rd_clk);
-				clk_domain_str = stringf("%sedge %s", rd_clk_posedge ? "pos" : "neg", os.str().c_str());
-				if( clk_to_lof_body.count(clk_domain_str) == 0 )
-					clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
-			}
-			if (use_rd_clk && !rd_transparent)
-			{
-				// for clocked read ports make something like:
-				//   reg [..] temp_id;
-				//   always @(posedge clk)
-				//      if (rd_en) temp_id <= array_reg[r_addr];
-				//   assign r_data = temp_id;
-				std::string temp_id = next_auto_id();
-				lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_data.size() - 1, temp_id.c_str()) );
 				{
 					std::ostringstream os;
-					if (sig_rd_en != RTLIL::SigBit(true))
+					dump_sigspec(os, sig_rd_clk);
+					clk_domain_str = stringf("%sedge %s", rd_clk_posedge ? "pos" : "neg", os.str().c_str());
+					if( clk_to_lof_body.count(clk_domain_str) == 0 )
+						clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
+				}
+				if (!rd_transparent)
+				{
+					// for clocked read ports make something like:
+					//   reg [..] temp_id;
+					//   always @(posedge clk)
+					//      if (rd_en) temp_id <= array_reg[r_addr];
+					//   assign r_data = temp_id;
+					std::string temp_id = next_auto_id();
+					lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_data.size() - 1, temp_id.c_str()) );
+					{
+						std::ostringstream os;
+						if (sig_rd_en != RTLIL::SigBit(true))
+						{
+							os << stringf("if (");
+							dump_sigspec(os, sig_rd_en);
+							os << stringf(") ");
+						}
+						os << stringf("%s <= %s[", temp_id.c_str(), mem_id.c_str());
+						dump_sigspec(os, sig_rd_addr);
+						os << stringf("];\n");
+						clk_to_lof_body[clk_domain_str].push_back(os.str());
+					}
 					{
-						os << stringf("if (");
-						dump_sigspec(os, sig_rd_en);
-						os << stringf(") ");
+						std::ostringstream os;
+						dump_sigspec(os, sig_rd_data);
+						std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
+						clk_to_lof_body[""].push_back(line);
 					}
-					os << stringf("%s <= %s[", temp_id.c_str(), mem_id.c_str());
-					dump_sigspec(os, sig_rd_addr);
-					os << stringf("];\n");
-					clk_to_lof_body[clk_domain_str].push_back(os.str());
 				}
+				else
 				{
-					std::ostringstream os;
-					dump_sigspec(os, sig_rd_data);
-					std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
-					clk_to_lof_body[""].push_back(line);
-				}
-			} else {
-				if (rd_transparent) {
 					// for rd-transparent read-ports make something like:
 					//   reg [..] temp_id;
 					//   always @(posedge clk)
@@ -1121,15 +1124,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 						std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
 						clk_to_lof_body[""].push_back(line);
 					}
-				} else {
-					// for non-clocked read-ports make something like:
-					//   assign r_data = array_reg[r_addr];
-					std::ostringstream os, os2;
-					dump_sigspec(os, sig_rd_data);
-					dump_sigspec(os2, sig_rd_addr);
-					std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
-					clk_to_lof_body[""].push_back(line);
 				}
+			} else {
+				// for non-clocked read-ports make something like:
+				//   assign r_data = array_reg[r_addr];
+				std::ostringstream os, os2;
+				dump_sigspec(os, sig_rd_data);
+				dump_sigspec(os2, sig_rd_addr);
+				std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
+				clk_to_lof_body[""].push_back(line);
 			}
 		}
 
-- 
cgit v1.2.3


From 8241db6960d17469678e8c71fd7d6c1b7ddc4fe7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:17:09 -0800
Subject: write_verilog to cope with init attr on q when -noexpr

---
 backends/verilog/verilog_backend.cc | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a7f329ef8..04191443a 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1247,7 +1247,30 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	dump_attributes(f, indent, cell->attributes);
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
-	if (!defparam && cell->parameters.size() > 0) {
+	std::string init;
+	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+		auto q_wire = cell->getPort("\\Q");
+
+		Const initval;
+		bool gotinit = false;
+
+		for (auto bit : active_sigmap(q_wire)) {
+			if (active_initdata.count(bit)) {
+				initval.bits.push_back(active_initdata.at(bit));
+				gotinit = true;
+			} else {
+				initval.bits.push_back(State::Sx);
+			}
+		}
+
+		if (gotinit) {
+			std::stringstream ss;
+			dump_const(ss, initval);
+			init = ss.str();
+		}
+	}
+
+	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		f << stringf(" #(");
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
@@ -1257,6 +1280,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(")");
 		}
+		if (!init.empty()) {
+			if (!cell->parameters.empty())
+				f << stringf(",");
+			f << stringf("\n%s  .INIT(%s)", indent.c_str(), init.c_str());
+		}
 		f << stringf("\n%s" ")", indent.c_str());
 	}
 
@@ -1298,13 +1326,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
-	if (defparam && cell->parameters.size() > 0) {
+	if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
 			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(";\n");
 		}
+		if (!init.empty())
+			f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
 	}
 
 }
-- 
cgit v1.2.3


From c373640a3ac6c2f76f0a8dce4e44236154ca24bc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:28:44 -0800
Subject: Refactor

---
 backends/verilog/verilog_backend.cc | 26 +++++---------------------
 1 file changed, 5 insertions(+), 21 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 04191443a..66a9e70d3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	}
 }
 
-void dump_reg_init(std::ostream &f, SigSpec sig)
+void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
 {
 	Const initval;
 	bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
 	}
 
 	if (gotinit) {
-		f << " = ";
+		if (write_equals) f << " = ";
 		dump_const(f, initval);
 	}
 }
@@ -1249,25 +1249,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	std::string init;
 	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
-		auto q_wire = cell->getPort("\\Q");
-
-		Const initval;
-		bool gotinit = false;
-
-		for (auto bit : active_sigmap(q_wire)) {
-			if (active_initdata.count(bit)) {
-				initval.bits.push_back(active_initdata.at(bit));
-				gotinit = true;
-			} else {
-				initval.bits.push_back(State::Sx);
-			}
-		}
-
-		if (gotinit) {
-			std::stringstream ss;
-			dump_const(ss, initval);
-			init = ss.str();
-		}
+		std::stringstream ss;
+		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
+		init = ss.str();
 	}
 
 	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
-- 
cgit v1.2.3


From 20ca795b87b810063cdcee6e92e3922281f6b092 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:53:40 -0800
Subject: Remove check for cell->name[0] == '$'

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 66a9e70d3..7b3a60e61 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
 	std::string init;
-	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
 		init = ss.str();
-- 
cgit v1.2.3


From 11480b4fa3ba031541e22b52d9ccd658a3e52ff1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 12:18:12 -0800
Subject: Instead of INIT param on cells, use initial statement with hier ref
 as per @cliffordwolf

---
 backends/verilog/verilog_backend.cc | 31 +++++++++++++------------------
 1 file changed, 13 insertions(+), 18 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 4b5a13941..d351a6266 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	}
 }
 
-void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
+void dump_reg_init(std::ostream &f, SigSpec sig)
 {
 	Const initval;
 	bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
 	}
 
 	if (gotinit) {
-		if (write_equals) f << " = ";
+		f << " = ";
 		dump_const(f, initval);
 	}
 }
@@ -1250,14 +1250,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	dump_attributes(f, indent, cell->attributes);
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
-	std::string init;
-	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
-		std::stringstream ss;
-		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
-		init = ss.str();
-	}
-
-	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
+	if (!defparam && cell->parameters.size() > 0) {
 		f << stringf(" #(");
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
@@ -1267,11 +1260,6 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(")");
 		}
-		if (!init.empty()) {
-			if (!cell->parameters.empty())
-				f << stringf(",");
-			f << stringf("\n%s  .INIT(%s)", indent.c_str(), init.c_str());
-		}
 		f << stringf("\n%s" ")", indent.c_str());
 	}
 
@@ -1313,17 +1301,24 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
-	if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
+	if (defparam && cell->parameters.size() > 0) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
 			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(";\n");
 		}
-		if (!init.empty())
-			f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
 	}
 
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+		std::stringstream ss;
+		dump_reg_init(ss, cell->getPort("\\Q"));
+		if (!ss.str().empty()) {
+			f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str());
+			f << ss.str();
+			f << ";\n";
+		}
+	}
 }
 
 void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
-- 
cgit v1.2.3


From 241901461ae02c6a41837e254088f277b8167476 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 14:56:55 -0800
Subject: Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d351a6266..6818edb7a 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -33,7 +33,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal;
+bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
 int auto_name_counter, auto_name_offset, auto_name_digits;
 std::map<RTLIL::IdString, int> auto_name_map;
 std::set<RTLIL::IdString> reg_wires, reg_ct;
@@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 	}
 
-	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"));
 		if (!ss.str().empty()) {
@@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend {
 		log("        without this option all internal cells are converted to Verilog\n");
 		log("        expressions.\n");
 		log("\n");
+		log("    -siminit\n");
+		log("        add initial statements with hierarchical refs to initialize FFs when\n");
+		log("        in -noexpr mode.\n");
+		log("\n");
 		log("    -nodec\n");
 		log("        32-bit constant values are by default dumped as decimal numbers,\n");
 		log("        not bit pattern. This option deactivates this feature and instead\n");
@@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend {
 		nostr = false;
 		defparam = false;
 		decimal = false;
+		siminit = false;
 		auto_prefix = "";
 
 		bool blackboxes = false;
@@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend {
 				decimal = true;
 				continue;
 			}
+			if (arg == "-siminit") {
+				siminit = true;
+				continue;
+			}
 			if (arg == "-blackboxes") {
 				blackboxes = true;
 				continue;
-- 
cgit v1.2.3


From 20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 11 Mar 2019 20:12:28 +0100
Subject: Improve determinism of IdString DB for similar scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6818edb7a..83d83f488 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1673,6 +1673,8 @@ struct VerilogBackend : public Backend {
 		bool blackboxes = false;
 		bool selected = false;
 
+		auto_name_map.clear();
+		reg_wires.clear();
 		reg_ct.clear();
 
 		reg_ct.insert("$dff");
@@ -1779,6 +1781,8 @@ struct VerilogBackend : public Backend {
 			dump_module(*f, "", it->second);
 		}
 
+		auto_name_map.clear();
+		reg_wires.clear();
 		reg_ct.clear();
 	}
 } VerilogBackend;
-- 
cgit v1.2.3


From f4abc21d8ad79621cc24852bd76abf40a9d9f702 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 18 Apr 2019 17:42:12 +0200
Subject: Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 83d83f488..855409d0b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1770,7 +1770,7 @@ struct VerilogBackend : public Backend {
 
 		*f << stringf("/* Generated by %s */\n", yosys_version_str);
 		for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
-			if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
+			if (it->second->get_blackbox_attribute() != blackboxes)
 				continue;
 			if (selected && !design->selected_whole_module(it->first)) {
 				if (design->selected_module(it->first))
-- 
cgit v1.2.3


From 0e0c80fac883a6f512a94aecdc3c915b8cacb562 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 19:44:10 +0200
Subject: Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 855409d0b..9967482d6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
+	if (width == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (nostr)
 		goto dump_hex;
 	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
@@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
 
 void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 {
+	if (GetSize(sig) == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
 	} else {
-- 
cgit v1.2.3


From 0bf9d0087c43f9db3d56cb2bed17268def21eb67 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:35:14 +0200
Subject: Add support for $assert/$assume/$cover to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9967482d6..1c65e79b7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1242,6 +1242,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type.in("$assert", "$assume", "$cover"))
+	{
+		f << stringf("%s" "always @* if (", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(") %s(", cell->type.c_str()+1);
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(");\n");
+		return true;
+	}
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
 
-- 
cgit v1.2.3


From 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:49:55 +0200
Subject: Add $specify2/$specify3 support to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 47 +++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 1c65e79b7..6bb08fdb2 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1252,6 +1252,53 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type.in("$specify2", "$specify3"))
+	{
+		f << stringf("%s" "specify\n%s  ", indent.c_str(), indent.c_str());
+
+		SigSpec en = cell->getPort("\\EN");
+		if (en != State::S1) {
+			f << stringf("if (");
+			dump_sigspec(f, cell->getPort("\\EN"));
+			f << stringf(") ");
+		}
+
+		f << "(";
+		if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool())
+			f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge ");
+
+		dump_sigspec(f, cell->getPort("\\SRC"));
+
+		f << " ";
+		if (cell->getParam("\\SRC_DST_PEN").as_bool())
+			f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-");
+		f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> ");
+
+		if (cell->type == "$specify3") {
+			f << "(";
+			dump_sigspec(f, cell->getPort("\\DST"));
+			f << " ";
+			if (cell->getParam("\\DAT_DST_PEN").as_bool())
+				f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-");
+			f << ": ";
+			dump_sigspec(f, cell->getPort("\\DAT"));
+			f << ")";
+		} else {
+			dump_sigspec(f, cell->getPort("\\DST"));
+		}
+
+		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
+				cell->getParam("\\T_RISE_MIN").as_int(),
+				cell->getParam("\\T_RISE_AVG").as_int(),
+				cell->getParam("\\T_RISE_MAX").as_int(),
+				cell->getParam("\\T_FALL_MIN").as_int(),
+				cell->getParam("\\T_FALL_AVG").as_int(),
+				cell->getParam("\\T_FALL_MAX").as_int());
+
+		f << stringf("%s" "endspecify\n", indent.c_str());
+		return true;
+	}
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
 
-- 
cgit v1.2.3


From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 09:52:47 +0200
Subject: Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog
 std nomenclature

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6bb08fdb2..93eaa8feb 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1289,10 +1289,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
 				cell->getParam("\\T_RISE_MIN").as_int(),
-				cell->getParam("\\T_RISE_AVG").as_int(),
+				cell->getParam("\\T_RISE_TYP").as_int(),
 				cell->getParam("\\T_RISE_MAX").as_int(),
 				cell->getParam("\\T_FALL_MIN").as_int(),
-				cell->getParam("\\T_FALL_AVG").as_int(),
+				cell->getParam("\\T_FALL_TYP").as_int(),
 				cell->getParam("\\T_FALL_MAX").as_int());
 
 		f << stringf("%s" "endspecify\n", indent.c_str());
-- 
cgit v1.2.3


From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 08:46:24 +0200
Subject: Improve write_verilog specify support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 86 ++++++++++++++++++++++++++++++-------
 1 file changed, 71 insertions(+), 15 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 93eaa8feb..9fd4ccbc8 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -183,8 +183,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	return true;
 }
 
-void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false, bool escape_comment = false)
+void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool escape_comment = false)
 {
+	bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 	if (width < 0)
 		width = data.bits.size() - offset;
 	if (width == 0) {
@@ -275,7 +276,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			}
 		}
 	} else {
-		f << stringf("\"");
+		if ((data.flags & RTLIL::CONST_FLAG_REAL) == 0)
+			f << stringf("\"");
 		std::string str = data.decode_string();
 		for (size_t i = 0; i < str.size(); i++) {
 			if (str[i] == '\n')
@@ -293,7 +295,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			else
 				f << str[i];
 		}
-		f << stringf("\"");
+		if ((data.flags & RTLIL::CONST_FLAG_REAL) == 0)
+			f << stringf("\"");
 	}
 }
 
@@ -373,7 +376,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, false, attr2comment);
+			dump_const(f, it->second, -1, 0, false, attr2comment);
 		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
 	}
 }
@@ -1287,13 +1290,68 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_sigspec(f, cell->getPort("\\DST"));
 		}
 
-		f << stringf(") = (%d:%d:%d, %d:%d:%d);\n",
-				cell->getParam("\\T_RISE_MIN").as_int(),
-				cell->getParam("\\T_RISE_TYP").as_int(),
-				cell->getParam("\\T_RISE_MAX").as_int(),
-				cell->getParam("\\T_FALL_MIN").as_int(),
-				cell->getParam("\\T_FALL_TYP").as_int(),
-				cell->getParam("\\T_FALL_MAX").as_int());
+		bool bak_decimal = decimal;
+		decimal = 1;
+
+		f << ") = (";
+		dump_const(f, cell->getParam("\\T_RISE_MIN"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_RISE_TYP"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_RISE_MAX"));
+		f << ", ";
+		dump_const(f, cell->getParam("\\T_FALL_MIN"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_FALL_TYP"));
+		f << ":";
+		dump_const(f, cell->getParam("\\T_FALL_MAX"));
+		f << ");\n";
+
+		decimal = bak_decimal;
+
+		f << stringf("%s" "endspecify\n", indent.c_str());
+		return true;
+	}
+
+	if (cell->type == "$specrule")
+	{
+		f << stringf("%s" "specify\n%s  ", indent.c_str(), indent.c_str());
+
+		string spec_type = cell->getParam("\\TYPE").decode_string();
+		f << stringf("%s(", spec_type.c_str());
+
+		if (cell->getParam("\\SRC_PEN").as_bool())
+			f << (cell->getParam("\\SRC_POL").as_bool() ? "posedge ": "negedge ");
+		dump_sigspec(f, cell->getPort("\\SRC"));
+
+		if (cell->getPort("\\SRC_EN") != State::S1) {
+			f << " &&& ";
+			dump_sigspec(f, cell->getPort("\\SRC_EN"));
+		}
+
+		f << ", ";
+		if (cell->getParam("\\DST_PEN").as_bool())
+			f << (cell->getParam("\\DST_POL").as_bool() ? "posedge ": "negedge ");
+		dump_sigspec(f, cell->getPort("\\DST"));
+
+		if (cell->getPort("\\DST_EN") != State::S1) {
+			f << " &&& ";
+			dump_sigspec(f, cell->getPort("\\DST_EN"));
+		}
+
+		bool bak_decimal = decimal;
+		decimal = 1;
+
+		f << ", ";
+		dump_const(f, cell->getParam("\\T_LIMIT"));
+
+		if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") {
+			f << ", ";
+			dump_const(f, cell->getParam("\\T_LIMIT2"));
+		}
+
+		f << ");\n";
+		decimal = bak_decimal;
 
 		f << stringf("%s" "endspecify\n", indent.c_str());
 		return true;
@@ -1321,8 +1379,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			if (it != cell->parameters.begin())
 				f << stringf(",");
 			f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
-			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
-			dump_const(f, it->second, -1, 0, false, is_signed);
+			dump_const(f, it->second);
 			f << stringf(")");
 		}
 		f << stringf("\n%s" ")", indent.c_str());
@@ -1369,8 +1426,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	if (defparam && cell->parameters.size() > 0) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
-			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
-			dump_const(f, it->second, -1, 0, false, is_signed);
+			dump_const(f, it->second);
 			f << stringf(";\n");
 		}
 	}
-- 
cgit v1.2.3


From 33738c174560c718723b6c860af002d1a8a91cea Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 7 May 2019 19:55:36 +0200
Subject: Fix handling of partial init attributes in write_verilog, fixes #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9fd4ccbc8..827af5d85 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1618,7 +1618,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 			SigSpec sig = active_sigmap(wire);
 			Const val = wire->attributes.at("\\init");
 			for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
-				active_initdata[sig[i]] = val.bits.at(i);
+				if (val[i] == State::S0 || val[i] == State::S1)
+					active_initdata[sig[i]] = val[i];
 		}
 
 	if (!module->processes.empty())
-- 
cgit v1.2.3


From 55c1f4027794a89971055b705254832b189a1c83 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 8 Jul 2019 12:48:50 +0000
Subject: verilog_backend: dump attributes on CaseRule, as comments.

Attributes are not permitted in that position by Verilog grammar.
---
 backends/verilog/verilog_backend.cc | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 827af5d85..18c92521f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -364,20 +364,22 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
+	if (attr2comment)
+		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
-		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
+		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
 		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
 			f << stringf(" 0 ");
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, attr2comment);
-		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
+			dump_const(f, it->second, -1, 0, false, as_comment);
+		f << stringf(" %s%c", as_comment ? "*/" : "*)", term);
 	}
 }
 
@@ -1511,7 +1513,9 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":\n");
+		f << stringf(":");
+		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
+		f << stringf("\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 
@@ -1662,7 +1666,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 	}
 
-	dump_attributes(f, indent, module->attributes, '\n', true);
+	dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true);
 	f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
-- 
cgit v1.2.3


From 628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 8 Jul 2019 15:11:29 +0000
Subject: verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.
---
 backends/verilog/verilog_backend.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 18c92521f..6288502a5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1494,6 +1494,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
-- 
cgit v1.2.3


From 6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 9 Jul 2019 18:30:24 +0000
Subject: write_verilog: write RTLIL::Sa aka - as Verilog ?.

Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
---
 backends/verilog/verilog_backend.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6288502a5..1c68288ce 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -222,7 +222,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 				case RTLIL::S1: bin_digits.push_back('1'); break;
 				case RTLIL::Sx: bin_digits.push_back('x'); break;
 				case RTLIL::Sz: bin_digits.push_back('z'); break;
-				case RTLIL::Sa: bin_digits.push_back('z'); break;
+				case RTLIL::Sa: bin_digits.push_back('?'); break;
 				case RTLIL::Sm: log_error("Found marker state in final netlist.");
 				}
 			}
@@ -251,6 +251,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 					hex_digits.push_back('z');
 					continue;
 				}
+				if (bit_3 == '?' || bit_2 == '?' || bit_1 == '?' || bit_0 == '?') {
+					if (bit_3 != '?' || bit_2 != '?' || bit_1 != '?' || bit_0 != '?')
+						goto dump_bin;
+					hex_digits.push_back('?');
+					continue;
+				}
 				int val = 8*(bit_3 - '0') + 4*(bit_2 - '0') + 2*(bit_1 - '0') + (bit_0 - '0');
 				hex_digits.push_back(val < 10 ? '0' + val : 'a' + val - 10);
 			}
@@ -270,7 +276,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 				case RTLIL::S1: f << stringf("1"); break;
 				case RTLIL::Sx: f << stringf("x"); break;
 				case RTLIL::Sz: f << stringf("z"); break;
-				case RTLIL::Sa: f << stringf("z"); break;
+				case RTLIL::Sa: f << stringf("?"); break;
 				case RTLIL::Sm: log_error("Found marker state in final netlist.");
 				}
 			}
-- 
cgit v1.2.3


From 37bb6b5e96fcedc1126c31aac84b8c029e192f5f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 9 Jul 2019 19:14:03 +0000
Subject: write_verilog: fix placement of case attributes. NFC.

---
 backends/verilog/verilog_backend.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6288502a5..087c6fec6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 
 	bool got_default = false;
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+		dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
 		if ((*it)->compare.size() == 0) {
 			if (got_default)
 				continue;
@@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 				dump_sigspec(f, (*it)->compare[i]);
 			}
 		}
-		f << stringf(":");
-		dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
-		f << stringf("\n");
+		f << stringf(":\n");
 		dump_case_body(f, indent + "    ", *it);
 	}
 
-- 
cgit v1.2.3


From 4ff44d85a5cb63c7b3f67c2f2398e62db7f199eb Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 16 Jul 2019 20:57:05 +0000
Subject: write_verilog: dump zero width constants correctly.

Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
---
 backends/verilog/verilog_backend.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a020d82b6..48404b34c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -189,7 +189,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	if (width < 0)
 		width = data.bits.size() - offset;
 	if (width == 0) {
-		f << "\"\"";
+		// See IEEE 1364-2005 Clause 5.1.14.
+		f << "{0{1'b0}}";
 		return;
 	}
 	if (nostr)
-- 
cgit v1.2.3


From 56c00e871fbb73649d3b6f7ccee31c90942a020c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 17 Jul 2019 11:49:04 +0200
Subject: Remove old $pmux_safe code from write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a020d82b6..778f9b855 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -788,7 +788,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$pmux" || cell->type == "$pmux_safe")
+	if (cell->type == "$pmux")
 	{
 		int width = cell->parameters["\\WIDTH"].as_int();
 		int s_width = cell->getPort("\\S").size();
@@ -800,18 +800,17 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf("%s" "  input [%d:0] s;\n", indent.c_str(), s_width-1);
 
 		dump_attributes(f, indent + "  ", cell->attributes);
-		if (cell->type != "$pmux_safe" && !noattr)
+		if (!noattr)
 			f << stringf("%s" "  (* parallel_case *)\n", indent.c_str());
 		f << stringf("%s" "  casez (s)", indent.c_str());
-		if (cell->type != "$pmux_safe")
-			f << stringf(noattr ? " // synopsys parallel_case\n" : "\n");
+		f << stringf(noattr ? " // synopsys parallel_case\n" : "\n");
 
 		for (int i = 0; i < s_width; i++)
 		{
 			f << stringf("%s" "    %d'b", indent.c_str(), s_width);
 
 			for (int j = s_width-1; j >= 0; j--)
-				f << stringf("%c", j == i ? '1' : cell->type == "$pmux_safe" ? '0' : '?');
+				f << stringf("%c", j == i ? '1' : '?');
 
 			f << stringf(":\n");
 			f << stringf("%s" "      %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width);
-- 
cgit v1.2.3


From 023086bd46bc828621ebb171b159efe1398aaecf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 Aug 2019 04:47:55 +0200
Subject: Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e0b3a6f80..776f4eacb 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -558,6 +558,20 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$_NMUX_") {
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = !(");
+		dump_cell_expr_port(f, cell, "S", false);
+		f << stringf(" ? ");
+		dump_attributes(f, "", cell->attributes, ' ');
+		dump_cell_expr_port(f, cell, "B", false);
+		f << stringf(" : ");
+		dump_cell_expr_port(f, cell, "A", false);
+		f << stringf(");\n");
+		return true;
+	}
+
 	if (cell->type.in("$_AOI3_", "$_OAI3_")) {
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort("\\Y"));
-- 
cgit v1.2.3


From 3486235338faa1377bb4e1a8981a45b4ee6edfa9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:18:18 -0700
Subject: Make liberal use of IdString.in()

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 776f4eacb..9a797b535 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -949,7 +949,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffe")
+	if (cell->type.in("$dff", "$adff", "$dffe"))
 	{
 		RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
 		bool pol_clk, pol_arst = false, pol_en = false;
-- 
cgit v1.2.3


From 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:22:47 -0700
Subject: Use State::S{0,1}

---
 backends/verilog/verilog_backend.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9a797b535..6cb053f1d 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -380,9 +380,9 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
 		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
-		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
+		if (modattr && (it->second == State::S0 || it->second == Const(0)))
 			f << stringf(" 0 ");
-		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
+		else if (modattr && (it->second == State::S1 || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
 			dump_const(f, it->second, -1, 0, false, as_comment);
-- 
cgit v1.2.3


From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:12:38 -0700
Subject: RTLIL::S{0,1} -> State::S{0,1}

---
 backends/verilog/verilog_backend.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6cb053f1d..6065a71ff 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -200,9 +200,9 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			int32_t val = 0;
 			for (int i = offset+width-1; i >= offset; i--) {
 				log_assert(i < (int)data.bits.size());
-				if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
+				if (data.bits[i] != State::S0 && data.bits[i] != State::S1)
 					goto dump_hex;
-				if (data.bits[i] == RTLIL::S1)
+				if (data.bits[i] == State::S1)
 					val |= 1 << (i - offset);
 			}
 			if (decimal)
@@ -219,8 +219,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			for (int i = offset; i < offset+width; i++) {
 				log_assert(i < (int)data.bits.size());
 				switch (data.bits[i]) {
-				case RTLIL::S0: bin_digits.push_back('0'); break;
-				case RTLIL::S1: bin_digits.push_back('1'); break;
+				case State::S0: bin_digits.push_back('0'); break;
+				case State::S1: bin_digits.push_back('1'); break;
 				case RTLIL::Sx: bin_digits.push_back('x'); break;
 				case RTLIL::Sz: bin_digits.push_back('z'); break;
 				case RTLIL::Sa: bin_digits.push_back('?'); break;
@@ -273,8 +273,8 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			for (int i = offset+width-1; i >= offset; i--) {
 				log_assert(i < (int)data.bits.size());
 				switch (data.bits[i]) {
-				case RTLIL::S0: f << stringf("0"); break;
-				case RTLIL::S1: f << stringf("1"); break;
+				case State::S0: f << stringf("0"); break;
+				case State::S1: f << stringf("1"); break;
 				case RTLIL::Sx: f << stringf("x"); break;
 				case RTLIL::Sz: f << stringf("z"); break;
 				case RTLIL::Sa: f << stringf("?"); break;
-- 
cgit v1.2.3


From 6d77236f3845cd8785e7bdd4da3c5ef966be6043 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 12:20:08 -0700
Subject: substr() -> compare()

---
 backends/verilog/verilog_backend.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/verilog')

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6065a71ff..7b1db4776 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -604,7 +604,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.substr(0, 6) == "$_DFF_")
+	if (cell->type.begins_with("$_DFF_"))
 	{
 		std::string reg_name = cellname(cell);
 		bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
@@ -645,7 +645,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type.substr(0, 8) == "$_DFFSR_")
+	if (cell->type.begins_with("$_DFFSR_"))
 	{
 		char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
 
-- 
cgit v1.2.3