From cbaba62401ca975bc9aee91b53e0b48fa59bd6c3 Mon Sep 17 00:00:00 2001 From: dh73 Date: Sun, 1 Oct 2017 11:04:17 -0500 Subject: Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now --- backends/verilog/verilog_backend.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bb312944e..33f9a81e4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -33,7 +33,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, nobasenradix; int auto_name_counter, auto_name_offset, auto_name_digits; std::map auto_name_map; std::set reg_wires, reg_ct; @@ -174,8 +174,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o } if (set_signed && val < 0) f << stringf("-32'sd%u", -val); - else - f << stringf("32'%sd%u", set_signed ? "s" : "", val); + else { + if(!nobasenradix) + f << stringf("%u", val); // There's no signed parameter on megawizard IP + else + f << stringf("32'%sd%u", set_signed ? "s" : "", val); + } } else { dump_hex: if (nohex) @@ -1485,6 +1489,10 @@ struct VerilogBackend : public Backend { log(" -v\n"); log(" verbose output (print new names of all renamed wires and cells)\n"); log("\n"); + log(" -nobasenradix\n"); + log(" dump defparam constants without size and radix for align with legacy\n"); + log(" MegaWizard primitive template implementation.\n"); + log("\n"); log("Note that RTLIL processes can't always be mapped directly to Verilog\n"); log("always blocks. This frontend should only be used to export an RTLIL\n"); log("netlist, i.e. after the \"proc\" pass has been used to convert all\n"); @@ -1505,6 +1513,7 @@ struct VerilogBackend : public Backend { nohex = false; nostr = false; defparam = false; + nobasenradix= false; auto_prefix = ""; bool blackboxes = false; @@ -1575,6 +1584,10 @@ struct VerilogBackend : public Backend { defparam = true; continue; } + if (arg == "-nobasenradix") { + defparam = true; + continue; + } if (arg == "-blackboxes") { blackboxes = true; continue; -- cgit v1.2.3 From e4808477531d31284244188637af3ccf89a21269 Mon Sep 17 00:00:00 2001 From: dh73 Date: Sun, 1 Oct 2017 11:11:32 -0500 Subject: Fixed wrong declaration in Verilog backend --- backends/verilog/verilog_backend.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 33f9a81e4..48e06dc7c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -175,7 +175,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o if (set_signed && val < 0) f << stringf("-32'sd%u", -val); else { - if(!nobasenradix) + if(nobasenradix) f << stringf("%u", val); // There's no signed parameter on megawizard IP else f << stringf("32'%sd%u", set_signed ? "s" : "", val); @@ -1585,8 +1585,8 @@ struct VerilogBackend : public Backend { continue; } if (arg == "-nobasenradix") { - defparam = true; - continue; + nobasenradix = true; + continue; } if (arg == "-blackboxes") { blackboxes = true; -- cgit v1.2.3 From 65f91e51205fdd436c569c4795517160960ac700 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 3 Oct 2017 17:31:21 +0200 Subject: Rename "write_verilog -nobasenradix" to "write_verilog -decimal" --- backends/verilog/verilog_backend.cc | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 48e06dc7c..fb0add847 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -33,7 +33,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, nobasenradix; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal; int auto_name_counter, auto_name_offset, auto_name_digits; std::map auto_name_map; std::set reg_wires, reg_ct; @@ -172,14 +172,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o if (data.bits[i] == RTLIL::S1) val |= 1 << (i - offset); } - if (set_signed && val < 0) + if (decimal) + f << stringf("%d", val); + else if (set_signed && val < 0) f << stringf("-32'sd%u", -val); - else { - if(nobasenradix) - f << stringf("%u", val); // There's no signed parameter on megawizard IP - else - f << stringf("32'%sd%u", set_signed ? "s" : "", val); - } + else + f << stringf("32'%sd%u", set_signed ? "s" : "", val); } else { dump_hex: if (nohex) @@ -1462,6 +1460,9 @@ struct VerilogBackend : public Backend { log(" not bit pattern. This option decativates this feature and instead\n"); log(" will write out all constants in binary.\n"); log("\n"); + log(" -decimal\n"); + log(" dump 32-bit constants in decimal and without size and radix\n"); + log("\n"); log(" -nohex\n"); log(" constant values that are compatible with hex output are usually\n"); log(" dumped as hex values. This option decativates this feature and\n"); @@ -1489,10 +1490,6 @@ struct VerilogBackend : public Backend { log(" -v\n"); log(" verbose output (print new names of all renamed wires and cells)\n"); log("\n"); - log(" -nobasenradix\n"); - log(" dump defparam constants without size and radix for align with legacy\n"); - log(" MegaWizard primitive template implementation.\n"); - log("\n"); log("Note that RTLIL processes can't always be mapped directly to Verilog\n"); log("always blocks. This frontend should only be used to export an RTLIL\n"); log("netlist, i.e. after the \"proc\" pass has been used to convert all\n"); @@ -1513,7 +1510,7 @@ struct VerilogBackend : public Backend { nohex = false; nostr = false; defparam = false; - nobasenradix= false; + decimal = false; auto_prefix = ""; bool blackboxes = false; @@ -1584,9 +1581,9 @@ struct VerilogBackend : public Backend { defparam = true; continue; } - if (arg == "-nobasenradix") { - nobasenradix = true; - continue; + if (arg == "-decimal") { + decimal = true; + continue; } if (arg == "-blackboxes") { blackboxes = true; -- cgit v1.2.3