From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- backends/spice/spice.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/spice') diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index ab5316ec3..a445e9cc9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -79,8 +79,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->has(wire->name)) { - sig = sigmap(cell->get(wire->name)); + if (cell->hasPort(wire->name)) { + sig = sigmap(cell->getPort(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); -- cgit v1.2.3