From f3ff29d4107355f5a1941da67e6402644dffefa4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 21 Feb 2014 13:10:36 +0100 Subject: Fixed instantiating multi-bit ports in edif backend --- backends/edif/edif.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 1748ed810..5020cd67e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -303,8 +303,10 @@ struct EdifBackend : public Backend { sig.expand(); for (int i = 0; i < sig.width; i++) { RTLIL::SigSpec sigbit(sig.chunks.at(i)); - std::string portname = sig.width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(p.first), i) : RTLIL::id2cstr(p.first); - net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(portname).c_str(), EDIF_NAME(cell->name))); + if (sig.width == 1) + net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), EDIF_NAME(cell->name))); + else + net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), i, EDIF_NAME(cell->name))); } } } -- cgit v1.2.3 From 038eac741415c3d7ddef3a1e9348586e7ba3d4ad Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 21 Feb 2014 13:40:43 +0100 Subject: Better handling of nameDef and nameRef in edif backend --- backends/edif/edif.cc | 48 +++++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 21 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 5020cd67e..8ac7cc7b2 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -28,7 +28,8 @@ #include #include -#define EDIF_NAME(_id) edif_names(RTLIL::unescape_id(_id)).c_str() +#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() +#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() namespace { @@ -40,8 +41,13 @@ namespace EdifNames() : counter(1) { } - std::string operator()(std::string id) + std::string operator()(std::string id, bool define) { + if (define) { + std::string new_id = operator()(id, false); + return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; + } + if (name_map.count(id) > 0) return name_map.at(id); if (generated_names.count(id) > 0) @@ -74,7 +80,7 @@ namespace } generated_names.insert(gen_name); name_map[id] = gen_name; - return stringf("(rename %s \"%s\")", gen_name.c_str(), id.c_str()); + return gen_name; } }; } @@ -155,7 +161,7 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) log_error("No module found in design!\n"); - fprintf(f, "(edif %s\n", EDIF_NAME(top_module_name)); + fprintf(f, "(edif %s\n", EDIF_DEF(top_module_name)); fprintf(f, " (edifVersion 2 0 0)\n"); fprintf(f, " (edifLevel 0)\n"); fprintf(f, " (keywordMap (keywordLevel 0))\n"); @@ -182,7 +188,7 @@ struct EdifBackend : public Backend { fprintf(f, " )\n"); for (auto &cell_it : lib_cell_ports) { - fprintf(f, " (cell %s\n", EDIF_NAME(cell_it.first)); + fprintf(f, " (cell %s\n", EDIF_DEF(cell_it.first)); fprintf(f, " (cellType GENERIC)\n"); fprintf(f, " (view VIEW_NETLIST\n"); fprintf(f, " (viewType NETLIST)\n"); @@ -195,7 +201,7 @@ struct EdifBackend : public Backend { else if (!ct.cell_input(cell_it.first, port_it)) dir = "OUTPUT"; } - fprintf(f, " (port %s (direction %s))\n", EDIF_NAME(port_it), dir); + fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(port_it), dir); } fprintf(f, " )\n"); fprintf(f, " )\n"); @@ -244,7 +250,7 @@ struct EdifBackend : public Backend { SigMap sigmap(module); std::map> net_join_db; - fprintf(f, " (cell %s\n", EDIF_NAME(module->name)); + fprintf(f, " (cell %s\n", EDIF_DEF(module->name)); fprintf(f, " (cellType GENERIC)\n"); fprintf(f, " (view VIEW_NETLIST\n"); fprintf(f, " (viewType NETLIST)\n"); @@ -259,14 +265,14 @@ struct EdifBackend : public Backend { else if (!wire->port_input) dir = "OUTPUT"; if (wire->width == 1) { - fprintf(f, " (port %s (direction %s))\n", EDIF_NAME(wire->name), dir); + fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); - net_join_db[sig].insert(stringf("(portRef %s)", EDIF_NAME(wire->name))); + net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_NAME(wire->name), wire->width, dir); + fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i)); - net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_NAME(wire->name), i)); + net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } } @@ -276,14 +282,14 @@ struct EdifBackend : public Backend { fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - fprintf(f, " (instance %s\n", EDIF_NAME(cell->name)); - fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type), + fprintf(f, " (instance %s\n", EDIF_DEF(cell->name)); + fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); for (auto &p : cell->parameters) if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0) - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.decode_string().c_str()); + fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str()); else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) - fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int()); + fprintf(f, "\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int()); else { std::string hex_string = ""; for (size_t i = 0; i < p.second.bits.size(); i += 4) { @@ -295,7 +301,7 @@ struct EdifBackend : public Backend { char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str()); + fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } fprintf(f, ")\n"); for (auto &p : cell->connections) { @@ -304,9 +310,9 @@ struct EdifBackend : public Backend { for (int i = 0; i < sig.width; i++) { RTLIL::SigSpec sigbit(sig.chunks.at(i)); if (sig.width == 1) - net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), EDIF_NAME(cell->name))); + net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else - net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", edif_names(RTLIL::id2cstr(p.first)).c_str(), i, EDIF_NAME(cell->name))); + net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); } } } @@ -322,7 +328,7 @@ struct EdifBackend : public Backend { for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') netname.erase(netname.begin() + i--); - fprintf(f, " (net %s (joined\n", edif_names(netname).c_str()); + fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); if (sig.chunks.at(0).wire == NULL) { @@ -339,8 +345,8 @@ struct EdifBackend : public Backend { } fprintf(f, " )\n"); - fprintf(f, " (design %s\n", EDIF_NAME(top_module_name)); - fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_NAME(top_module_name)); + fprintf(f, " (design %s\n", EDIF_DEF(top_module_name)); + fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); fprintf(f, " )\n"); fprintf(f, ")\n"); -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- backends/edif/edif.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 8ac7cc7b2..c239ef306 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -149,7 +149,7 @@ struct EdifBackend : public Backend { if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; for (auto p : cell->connections) { - if (p.second.width > 1) + if (p.second.__width > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); lib_cell_ports[cell->type].insert(p.first); @@ -307,9 +307,9 @@ struct EdifBackend : public Backend { for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); sig.expand(); - for (int i = 0; i < sig.width; i++) { - RTLIL::SigSpec sigbit(sig.chunks.at(i)); - if (sig.width == 1) + for (int i = 0; i < sig.__width; i++) { + RTLIL::SigSpec sigbit(sig.__chunks.at(i)); + if (sig.__width == 1) net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); @@ -319,9 +319,9 @@ struct EdifBackend : public Backend { for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; sig.optimize(); - log_assert(sig.width == 1); - if (sig.chunks.at(0).wire == NULL) { - if (sig.chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks.at(0).data.bits.at(0) != RTLIL::State::S1) + log_assert(sig.__width == 1); + if (sig.__chunks.at(0).wire == NULL) { + if (sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S1) continue; } std::string netname = log_signal(sig); @@ -331,10 +331,10 @@ struct EdifBackend : public Backend { fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); - if (sig.chunks.at(0).wire == NULL) { - if (sig.chunks.at(0).data.bits.at(0) == RTLIL::State::S0) + if (sig.__chunks.at(0).wire == NULL) { + if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S0) fprintf(f, " (portRef G (instanceRef GND))\n"); - if (sig.chunks.at(0).data.bits.at(0) == RTLIL::State::S1) + if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1) fprintf(f, " (portRef P (instanceRef VCC))\n"); } fprintf(f, " ))\n"); -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- backends/edif/edif.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index c239ef306..bb2b26e26 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -149,7 +149,7 @@ struct EdifBackend : public Backend { if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; for (auto p : cell->connections) { - if (p.second.__width > 1) + if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); lib_cell_ports[cell->type].insert(p.first); @@ -307,9 +307,9 @@ struct EdifBackend : public Backend { for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); sig.expand(); - for (int i = 0; i < sig.__width; i++) { - RTLIL::SigSpec sigbit(sig.__chunks.at(i)); - if (sig.__width == 1) + for (int i = 0; i < sig.size(); i++) { + RTLIL::SigSpec sigbit(sig.chunks().at(i)); + if (sig.size() == 1) net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); @@ -319,9 +319,9 @@ struct EdifBackend : public Backend { for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; sig.optimize(); - log_assert(sig.__width == 1); - if (sig.__chunks.at(0).wire == NULL) { - if (sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S1) + log_assert(sig.size() == 1); + if (sig.chunks().at(0).wire == NULL) { + if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) continue; } std::string netname = log_signal(sig); @@ -331,10 +331,10 @@ struct EdifBackend : public Backend { fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); - if (sig.__chunks.at(0).wire == NULL) { - if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S0) + if (sig.chunks().at(0).wire == NULL) { + if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0) fprintf(f, " (portRef G (instanceRef GND))\n"); - if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1) + if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1) fprintf(f, " (portRef P (instanceRef VCC))\n"); } fprintf(f, " ))\n"); -- cgit v1.2.3 From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- backends/edif/edif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index bb2b26e26..f003c750d 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -271,7 +271,7 @@ struct EdifBackend : public Backend { } else { fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i)); + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } -- cgit v1.2.3 From ec923652e2eb721aa16657e54a67666f855c3d65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:48:26 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 --- backends/edif/edif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index f003c750d..74cf24997 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -271,7 +271,7 @@ struct EdifBackend : public Backend { } else { fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i)); + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } -- cgit v1.2.3 From a62c21c9c64ad5b3e0dae5d4ee4857425f73068e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 16:09:27 +0200 Subject: Removed RTLIL::SigSpec::expand() method --- backends/edif/edif.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 74cf24997..3b9a43370 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -306,14 +306,11 @@ struct EdifBackend : public Backend { fprintf(f, ")\n"); for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); - sig.expand(); - for (int i = 0; i < sig.size(); i++) { - RTLIL::SigSpec sigbit(sig.chunks().at(i)); + for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) - net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); + net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else - net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); - } + net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); } } for (auto &it : net_join_db) { -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- backends/edif/edif.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 3b9a43370..8f36f4090 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -315,7 +315,6 @@ struct EdifBackend : public Backend { } for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; - sig.optimize(); log_assert(sig.size() == 1); if (sig.chunks().at(0).wire == NULL) { if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- backends/edif/edif.cc | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 8f36f4090..a3ae9649e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -314,12 +314,9 @@ struct EdifBackend : public Backend { } } for (auto &it : net_join_db) { - RTLIL::SigSpec sig = it.first; - log_assert(sig.size() == 1); - if (sig.chunks().at(0).wire == NULL) { - if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) - continue; - } + RTLIL::SigBit sig = it.first; + if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) + continue; std::string netname = log_signal(sig); for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') @@ -327,10 +324,10 @@ struct EdifBackend : public Backend { fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); - if (sig.chunks().at(0).wire == NULL) { - if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0) + if (sig.wire == NULL) { + if (sig == RTLIL::State::S0) fprintf(f, " (portRef G (instanceRef GND))\n"); - if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1) + if (sig == RTLIL::State::S1) fprintf(f, " (portRef P (instanceRef VCC))\n"); } fprintf(f, " ))\n"); -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- backends/edif/edif.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index a3ae9649e..13ab4dc62 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -148,7 +148,7 @@ struct EdifBackend : public Backend { RTLIL::Cell *cell = cell_it.second; if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; - for (auto p : cell->connections) { + for (auto p : cell->connections_) { if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); @@ -304,7 +304,7 @@ struct EdifBackend : public Backend { fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } fprintf(f, ")\n"); - for (auto &p : cell->connections) { + for (auto &p : cell->connections_) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- backends/edif/edif.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 13ab4dc62..fc2f4a7e4 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -148,7 +148,7 @@ struct EdifBackend : public Backend { RTLIL::Cell *cell = cell_it.second; if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; - for (auto p : cell->connections_) { + for (auto p : cell->connections()) { if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); @@ -304,7 +304,7 @@ struct EdifBackend : public Backend { fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } fprintf(f, ")\n"); - for (auto &p : cell->connections_) { + for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/edif/edif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index fc2f4a7e4..e99d094f7 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -255,7 +255,7 @@ struct EdifBackend : public Backend { fprintf(f, " (view VIEW_NETLIST\n"); fprintf(f, " (viewType NETLIST)\n"); fprintf(f, " (interface\n"); - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) continue; -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- backends/edif/edif.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index e99d094f7..d23e99e7e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -143,7 +143,7 @@ struct EdifBackend : public Backend { if (module->memories.size() != 0) log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name)); - for (auto cell_it : module->cells) + for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { @@ -215,7 +215,7 @@ struct EdifBackend : public Backend { std::map> module_deps; for (auto &mod_it : design->modules) { module_deps[mod_it.second] = std::set(); - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (design->modules.count(cell_it.second->type) > 0) module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type)); } @@ -280,7 +280,7 @@ struct EdifBackend : public Backend { fprintf(f, " (contents\n"); fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; fprintf(f, " (instance %s\n", EDIF_DEF(cell->name)); fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- backends/edif/edif.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index d23e99e7e..5eff4598a 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -125,11 +125,11 @@ struct EdifBackend : public Backend { extra_args(f, filename, args, argidx); if (top_module_name.empty()) - for (auto & mod_it:design->modules) + for (auto & mod_it:design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_module_name = mod_it.first; - for (auto module_it : design->modules) + for (auto module_it : design->modules_) { RTLIL::Module *module = module_it.second; if (module->get_bool_attribute("\\blackbox")) @@ -146,7 +146,7 @@ struct EdifBackend : public Backend { for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { + if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; for (auto p : cell->connections()) { if (p.second.size() > 1) @@ -213,11 +213,11 @@ struct EdifBackend : public Backend { // extract module dependencies std::map> module_deps; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { module_deps[mod_it.second] = std::set(); for (auto &cell_it : mod_it.second->cells_) - if (design->modules.count(cell_it.second->type) > 0) - module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type)); + if (design->modules_.count(cell_it.second->type) > 0) + module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type)); } // simple good-enough topological sort -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- backends/edif/edif.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 5eff4598a..49f719a4a 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -26,7 +26,6 @@ #include "kernel/celltypes.h" #include "kernel/log.h" #include -#include #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- backends/edif/edif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 49f719a4a..bf1efc4ae 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -108,7 +108,7 @@ struct EdifBackend : public Backend { log_header("Executing EDIF backend.\n"); std::string top_module_name; - std::map> lib_cell_ports; + std::map> lib_cell_ports; CellTypes ct(design); EdifNames edif_names; -- cgit v1.2.3 From 04727c7e0fb4c00b38999da192e4ada2a6f9474a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 18:58:40 +0200 Subject: No implicit conversion from IdString to anything else --- backends/edif/edif.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index bf1efc4ae..ecdfaabfc 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -126,7 +126,7 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) for (auto & mod_it:design->modules_) if (mod_it.second->get_bool_attribute("\\top")) - top_module_name = mod_it.first; + top_module_name = mod_it.first.str(); for (auto module_it : design->modules_) { @@ -135,7 +135,7 @@ struct EdifBackend : public Backend { continue; if (top_module_name.empty()) - top_module_name = module->name; + top_module_name = module->name.str(); if (module->processes.size() != 0) log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name)); -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- backends/edif/edif.cc | 138 +++++++++++++++++++++++++------------------------- 1 file changed, 69 insertions(+), 69 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index ecdfaabfc..ccedd91d2 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -103,7 +103,7 @@ struct EdifBackend : public Backend { log("is targeted.\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { log_header("Executing EDIF backend.\n"); @@ -160,38 +160,38 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) log_error("No module found in design!\n"); - fprintf(f, "(edif %s\n", EDIF_DEF(top_module_name)); - fprintf(f, " (edifVersion 2 0 0)\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (keywordMap (keywordLevel 0))\n"); - fprintf(f, " (comment \"Generated by %s\")\n", yosys_version_str); - - fprintf(f, " (external LIB\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (technology (numberDefinition))\n"); - - fprintf(f, " (cell GND\n"); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface (port G (direction OUTPUT)))\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); - - fprintf(f, " (cell VCC\n"); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface (port P (direction OUTPUT)))\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf("(edif %s\n", EDIF_DEF(top_module_name)); + *f << stringf(" (edifVersion 2 0 0)\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (keywordMap (keywordLevel 0))\n"); + *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str); + + *f << stringf(" (external LIB\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (technology (numberDefinition))\n"); + + *f << stringf(" (cell GND\n"); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface (port G (direction OUTPUT)))\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + + *f << stringf(" (cell VCC\n"); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface (port P (direction OUTPUT)))\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); for (auto &cell_it : lib_cell_ports) { - fprintf(f, " (cell %s\n", EDIF_DEF(cell_it.first)); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface\n"); + *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first)); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface\n"); for (auto &port_it : cell_it.second) { const char *dir = "INOUT"; if (ct.cell_known(cell_it.first)) { @@ -200,13 +200,13 @@ struct EdifBackend : public Backend { else if (!ct.cell_input(cell_it.first, port_it)) dir = "OUTPUT"; } - fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(port_it), dir); + *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it), dir); } - fprintf(f, " )\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); } - fprintf(f, " )\n"); + *f << stringf(" )\n"); std::vector sorted_modules; @@ -238,9 +238,9 @@ struct EdifBackend : public Backend { } - fprintf(f, " (library DESIGN\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (technology (numberDefinition))\n"); + *f << stringf(" (library DESIGN\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (technology (numberDefinition))\n"); for (auto module : sorted_modules) { if (module->get_bool_attribute("\\blackbox")) @@ -249,11 +249,11 @@ struct EdifBackend : public Backend { SigMap sigmap(module); std::map> net_join_db; - fprintf(f, " (cell %s\n", EDIF_DEF(module->name)); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface\n"); + *f << stringf(" (cell %s\n", EDIF_DEF(module->name)); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface\n"); for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) @@ -264,31 +264,31 @@ struct EdifBackend : public Backend { else if (!wire->port_input) dir = "OUTPUT"; if (wire->width == 1) { - fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); + *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } } - fprintf(f, " )\n"); - fprintf(f, " (contents\n"); - fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); - fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); + *f << stringf(" )\n"); + *f << stringf(" (contents\n"); + *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); + *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - fprintf(f, " (instance %s\n", EDIF_DEF(cell->name)); - fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), + *f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); + *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); for (auto &p : cell->parameters) if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0) - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str()); + *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str()); else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) - fprintf(f, "\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int()); + *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int()); else { std::string hex_string = ""; for (size_t i = 0; i < p.second.bits.size(); i += 4) { @@ -300,9 +300,9 @@ struct EdifBackend : public Backend { char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); + *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } - fprintf(f, ")\n"); + *f << stringf(")\n"); for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) @@ -320,28 +320,28 @@ struct EdifBackend : public Backend { for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') netname.erase(netname.begin() + i--); - fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); + *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) - fprintf(f, " %s\n", ref.c_str()); + *f << stringf(" %s\n", ref.c_str()); if (sig.wire == NULL) { if (sig == RTLIL::State::S0) - fprintf(f, " (portRef G (instanceRef GND))\n"); + *f << stringf(" (portRef G (instanceRef GND))\n"); if (sig == RTLIL::State::S1) - fprintf(f, " (portRef P (instanceRef VCC))\n"); + *f << stringf(" (portRef P (instanceRef VCC))\n"); } - fprintf(f, " ))\n"); + *f << stringf(" ))\n"); } - fprintf(f, " )\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); } - fprintf(f, " )\n"); + *f << stringf(" )\n"); - fprintf(f, " (design %s\n", EDIF_DEF(top_module_name)); - fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); - fprintf(f, " )\n"); + *f << stringf(" (design %s\n", EDIF_DEF(top_module_name)); + *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); + *f << stringf(" )\n"); - fprintf(f, ")\n"); + *f << stringf(")\n"); } } EdifBackend; -- cgit v1.2.3