From e340532ce5d60129fbfb2e1b0a3eb916ec856b26 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Nov 2013 01:49:37 +0100 Subject: Added init= attribute for fpga-style reset values --- README | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README') diff --git a/README b/README index 9825bca45..eb60bc3fb 100644 --- a/README +++ b/README @@ -258,6 +258,10 @@ Verilog Attributes and non-standard features never be removed by the optimizer. This is used for example for cells that have hidden connections that are not part of the netlist, such as IO pads. +- The "init" attribute on wires is set by the frontend when a register is + initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis + to add the necessary reset logic. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset -- cgit v1.2.3