From 91704a78531bec2e3eea3ddf90eaedb28e1d696d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 11 Mar 2014 14:24:24 +0100 Subject: Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28) --- README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index 385ee2c0a..45febc2f9 100644 --- a/README +++ b/README @@ -292,7 +292,7 @@ a recent version of gcc: This is a bug in the minisat header. It can be fixed by adding spaces before and after each occurrence of PRIi64 in the header file: - sudo sed -i 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h + sudo sed -i -e 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h Roadmap / Large-scale TODOs -- cgit v1.2.3 From 94c1307c262e4b14f4a91b1bbcf9099ee6202bab Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 12 Mar 2014 10:17:51 +0100 Subject: Added libs/minisat (copy of minisat git master) --- README | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'README') diff --git a/README b/README index 45febc2f9..5a48a207c 100644 --- a/README +++ b/README @@ -280,21 +280,6 @@ Verilog Attributes and non-standard features must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 -Workarounds for known build problems -==================================== - -You might get an error message like this one during build when building with -a recent version of gcc: - - /usr/include/minisat/utils/Options.h:285:29: error: - unable to find string literal operator ‘operator"" PRIi64’ - -This is a bug in the minisat header. It can be fixed by adding spaces before -and after each occurrence of PRIi64 in the header file: - - sudo sed -i -e 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h - - Roadmap / Large-scale TODOs =========================== -- cgit v1.2.3 From 12a3c05229a958a4ff3fb8ad782ceb28bab6dca1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Apr 2014 10:19:46 +0200 Subject: Updated README --- README | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) (limited to 'README') diff --git a/README b/README index 5a48a207c..d021c8864 100644 --- a/README +++ b/README @@ -56,20 +56,15 @@ and TCL for the scripting functionality. The extensive test suite requires Icarus Verilog. For example on Ubuntu Linux 12.04 LTS the following commands will install all prerequisites for building yosys: - $ sudo apt-get install git - $ sudo apt-get install g++ - $ sudo apt-get install clang - $ sudo apt-get install make - $ sudo apt-get install bison - $ sudo apt-get install flex - $ sudo apt-get install libreadline-dev - $ sudo apt-get install tcl8.5-dev - $ sudo apt-get install minisat - $ sudo apt-get install zlib1g-dev - $ sudo apt-get install libqt4-dev - $ sudo apt-get install mercurial - $ sudo apt-get install iverilog - $ sudo apt-get install graphviz + $ yosys_deps="git g++ clang make bison flex libreadline-dev + tcl8.5-dev zlib1g-dev libqt4-dev mercurial + iverilog graphviz" + $ sudo apt-get install $yosys_deps + +There are also pre-compiled packages for Yosys on Ubuntu. Visit the Yosys +download page to learn more about this: + + http://www.clifford.at/yosys/download.html To configure the build system to use a specific set of compiler and build configuration, use one of @@ -82,7 +77,8 @@ For other compilers and build configurations it might be necessary to make some changes to the config section of the Makefile. - $ vi Makefile + $ vi Makefile ..or.. + $ vi Makefile.conf To build Yosys simply type 'make' in this directory. @@ -90,9 +86,6 @@ To build Yosys simply type 'make' in this directory. $ make test $ sudo make install -If you encounter any problems during build, make sure to check the section -"Workarounds for known build problems" at the end of this README file. - Note that this also downloads, builds and installs ABC (using yosys-abc as executeable name). -- cgit v1.2.3 From 482d9208aa9dacb7afe21f08c882d4881581013a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Jun 2014 11:54:20 +0200 Subject: Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch --- README | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'README') diff --git a/README b/README index d021c8864..05628a8e3 100644 --- a/README +++ b/README @@ -263,14 +263,24 @@ Verilog Attributes and non-standard features for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- Sized constants (the syntax 's?[bodh]) support constant + expressions as . If the expresion is not a simple identifier, it + must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 + + +Supported features from SystemVerilog +===================================== + +When read_verilog is called with -sv, it accepts some language features +from SystemVerilog: + - The "assert" statement from SystemVerilog is supported in its most basic form. In module context: "assert property ();" and within an always block: "assert();". It is transformed to a $assert cell that is supported by the "sat" and "write_btor" commands. -- Sized constants (the syntax 's?[bodh]) support constant - expressions as . If the expresion is not a simple identifier, it - must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 +- The keywords "always_comb", "always_ff" and "always_latch", "logic" and + "bit" are supported. Roadmap / Large-scale TODOs -- cgit v1.2.3 From b1b96d199f7d0b97d203e3fd60af698ebaf03d73 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 15 Jun 2014 11:51:51 +0200 Subject: Added more calls to "hierarchy" to README file --- README | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'README') diff --git a/README b/README index 05628a8e3..ba90e72a6 100644 --- a/README +++ b/README @@ -109,6 +109,10 @@ writing the design to the console in yosys's internal format: yosys> write_ilang +elaborate design hierarchy: + + yosys> hierarchy + convert processes ("always" blocks) to netlist elements and perform some simple optimizations: @@ -132,13 +136,14 @@ write design netlist to a new verilog file: a similar synthesis can be performed using yosys command line options only: - $ ./yosys -o synth.v -p proc -p opt -p techmap -p opt tests/simple/fiedler-cooley.v + $ ./yosys -o synth.v -p hierarchy -p proc -p opt \ + -p techmap -p opt tests/simple/fiedler-cooley.v or using a simple synthesis script: $ cat synth.ys read_verilog tests/simple/fiedler-cooley.v - proc; opt; techmap; opt + hierarchy; proc; opt; techmap; opt write_verilog synth.v $ ./yosys synth.ys @@ -147,7 +152,7 @@ It is also possible to only have the synthesis commands but not the read/write commands in the synthesis script: $ cat synth.ys - proc; opt; techmap; opt + hierarchy; proc; opt; techmap; opt $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys -- cgit v1.2.3 From 89c85cac419b7dc60e3776a250bcdc39dcb8980b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 28 Jun 2014 12:11:42 +0200 Subject: Added links to some liberty files to README --- README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'README') diff --git a/README b/README index ba90e72a6..4384cfbdd 100644 --- a/README +++ b/README @@ -192,6 +192,14 @@ for the given cell library: If you do not have a liberty file but want to test this synthesis script, you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources. +Various more complex liberty files (for testing) can be found here: + + http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/.. + ../cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib + ../cadence/lib/ami035/signalstorm/osu035_stdcells.lib + ../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib + ../cadence/lib/ami05/signalstorm/osu05_stdcells.lib + Yosys is under construction. A more detailed documentation will follow. -- cgit v1.2.3 From 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 02:32:00 +0200 Subject: Renamed "stdcells.v" to "techmap.v" --- README | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index 4384cfbdd..1e0ade91c 100644 --- a/README +++ b/README @@ -304,8 +304,7 @@ Roadmap / Large-scale TODOs - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Technology mapping for real-world applications - - Add bit-wise const-folding via cell parameters to techmap pass - - Rewrite current stdcells.v techmap rules (modular and clean) + - Rewrite current techmap.v rules (modular and clean) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Implement SAT-based formal equivialence checker -- cgit v1.2.3 From b5a3419ac2c6f367b90f062c4e2252029910cdb9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Aug 2014 15:19:24 +0200 Subject: Added support for non-standard "module mod_name(...);" syntax --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 1e0ade91c..63d692297 100644 --- a/README +++ b/README @@ -276,6 +276,11 @@ Verilog Attributes and non-standard features for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- Modules can be declared with "module mod_name(...);" (with three dots + instead of a list of moudle ports). With this syntax it is sufficient + to simply declare a module port as 'input' or 'output' in the module + body. + - Sized constants (the syntax 's?[bodh]) support constant expressions as . If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 -- cgit v1.2.3 From d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 6 Aug 2014 15:43:46 +0200 Subject: Added AST_MULTIRANGE (arrays with more than 1 dimension) --- README | 1 - 1 file changed, 1 deletion(-) (limited to 'README') diff --git a/README b/README index 63d692297..0c8425f37 100644 --- a/README +++ b/README @@ -326,7 +326,6 @@ Other Unsorted TODOs - Implement missing Verilog 2005 features: - - Multi-dimensional arrays - Support for real (float) const. expressions and parameters - ROM modeling using $readmemh/$readmemb in "initial" blocks - Ignore what needs to be ignored (e.g. drive and charge strengths) -- cgit v1.2.3 From f53984795d38946ee71684d88883cafd9f58f603 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Aug 2014 13:03:38 +0200 Subject: Added support for non-standard """ macro bodies --- README | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'README') diff --git a/README b/README index 0c8425f37..1ecaa07df 100644 --- a/README +++ b/README @@ -281,6 +281,15 @@ Verilog Attributes and non-standard features to simply declare a module port as 'input' or 'output' in the module body. +- When defining a macro with `define, all text between tripple double quotes + is interpreted as macro body, even if it contains unescaped newlines. The + tripple double quotes are removed from the macro body. For example: + + `define MY_MACRO(a, b) """ + assign a = 23; + assign b = 42; + """ + - Sized constants (the syntax 's?[bodh]) support constant expressions as . If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 -- cgit v1.2.3 From 640d9fc551c546b511f8d64c0ccfc438937164a1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 18 Aug 2014 14:29:30 +0200 Subject: Added "via_celltype" attribute on task/func --- README | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'README') diff --git a/README b/README index 1ecaa07df..a0e67e8a4 100644 --- a/README +++ b/README @@ -290,6 +290,33 @@ Verilog Attributes and non-standard features assign b = 42; """ +- The attribute "via_celltype" can be used to implement a verilog task or + function by instantiating the specified cell type. The value is the name + of the cell type to use. For functions the name of the output port can + be specified by appending it to the cell type separated by a whitespace. + The body of the task or function is unused in this case and can be used + to specify a behavioral model of the cell type for simulation. For example: + + module my_add3(A, B, C, Y); + parameter WIDTH = 8; + input [WIDTH-1:0] A, B, C; + output [WIDTH-1:0] Y; + ... + endmodule + + module top; + ... + (* via_celltype = "my_add3 Y" *) + (* via_celltype_defparam_WIDTH = 32 *) + function [31:0] add3; + input [31:0] A, B, C; + begin + add3 = A + B + C; + end + endfunction + ... + endmodule + - Sized constants (the syntax 's?[bodh]) support constant expressions as . If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 -- cgit v1.2.3 From 74af3a2b7086acad45d15b590a0d23572e8c8734 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 14:22:09 +0200 Subject: Archibald Rust and Clifford Wolf: ffi-based dpi_call() --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index a0e67e8a4..5c3286c20 100644 --- a/README +++ b/README @@ -57,8 +57,8 @@ Icarus Verilog. For example on Ubuntu Linux 12.04 LTS the following commands will install all prerequisites for building yosys: $ yosys_deps="git g++ clang make bison flex libreadline-dev - tcl8.5-dev zlib1g-dev libqt4-dev mercurial - iverilog graphviz" + tcl8.5-dev zlib1g-dev libqt4-dev libffi-dev + mercurial iverilog graphviz" $ sudo apt-get install $yosys_deps There are also pre-compiled packages for Yosys on Ubuntu. Visit the Yosys -- cgit v1.2.3 From ba83a7bdc641c68344b41f407323c76b8c62c674 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 14:37:14 +0200 Subject: Added DPI-C documentation to README file --- README | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'README') diff --git a/README b/README index 5c3286c20..2e713ffef 100644 --- a/README +++ b/README @@ -317,6 +317,18 @@ Verilog Attributes and non-standard features ... endmodule +- A limited subset of DPI-C functions is supported. The plugin mechanism + (see "help plugin") can be used load .so files with implementations of + DPI-C routines. As a non-standard extension it is possible to specify + a plugin alias using the ":" syntax. for example: + + module dpitest; + import "DPI-C" function foo:round = real my_round (real); + parameter real r = my_round(12.345); + endmodule + + $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' + - Sized constants (the syntax 's?[bodh]) support constant expressions as . If the expresion is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 -- cgit v1.2.3 From 9f00a0cd2d972a5fc4a75f8c1bdba723a5f66b7d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 03:28:46 +0200 Subject: Using "xdot" instead of "yosys-svgviewer" in show command --- README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index 2e713ffef..2c7703a15 100644 --- a/README +++ b/README @@ -58,7 +58,7 @@ will install all prerequisites for building yosys: $ yosys_deps="git g++ clang make bison flex libreadline-dev tcl8.5-dev zlib1g-dev libqt4-dev libffi-dev - mercurial iverilog graphviz" + mercurial iverilog graphviz xdot" $ sudo apt-get install $yosys_deps There are also pre-compiled packages for Yosys on Ubuntu. Visit the Yosys -- cgit v1.2.3 From ee29ae2206b913fbb8cd41782001eed24c53b39d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 03:52:46 +0200 Subject: Removed yosys-svgviewer --- README | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'README') diff --git a/README b/README index 2c7703a15..7e8a42a86 100644 --- a/README +++ b/README @@ -50,15 +50,13 @@ Getting Started You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. -The Qt4 library is needed for the yosys SVG viewer, that is used to display -schematics, the minisat library is required for the SAT features in yosys -and TCL for the scripting functionality. The extensive test suite requires -Icarus Verilog. For example on Ubuntu Linux 12.04 LTS the following commands -will install all prerequisites for building yosys: - - $ yosys_deps="git g++ clang make bison flex libreadline-dev - tcl8.5-dev zlib1g-dev libqt4-dev libffi-dev - mercurial iverilog graphviz xdot" +TCL, readline and libffi are optional (see ENABLE_* settings in Makefile). +Xdot (graphviz) is used by the "show" command in yosys to display schematics. +For example on Ubuntu Linux 14.04 LTS the following commands will install all +prerequisites for building yosys: + + $ yosys_deps="build-essential clang bison flex libreadline-dev + tcl8.5-dev libffi-dev git mercurial graphviz xdot" $ sudo apt-get install $yosys_deps There are also pre-compiled packages for Yosys on Ubuntu. Visit the Yosys @@ -66,12 +64,10 @@ download page to learn more about this: http://www.clifford.at/yosys/download.html -To configure the build system to use a specific set of compiler and -build configuration, use one of +To configure the build system to use a specific compiler, use one of - $ make config-clang-debug - $ make config-gcc-debug - $ make config-release + $ make config-clang + $ make config-gcc For other compilers and build configurations it might be necessary to make some changes to the config section of the @@ -118,7 +114,7 @@ some simple optimizations: yosys> proc; opt -display design netlist using the yosys svg viewer: +display design netlist using xdot: yosys> show @@ -156,17 +152,20 @@ commands in the synthesis script: $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys -The following synthesis script works reasonable for all designs: +The following very basic synthesis script should work well with all designs: # check design hierarchy hierarchy - # translate processes (always blocks) and memories (arrays) - proc; memory; opt + # translate processes (always blocks) + proc; opt # detect and optimize FSM encodings fsm; opt + # implement memories (arrays) + memory; opt + # convert to gate logic techmap; opt @@ -175,7 +174,7 @@ in the liberty file mycells.lib, the following synthesis script will synthesize for the given cell library: # the high-level stuff - hierarchy; proc; memory; opt; fsm; opt + hierarchy; proc; fsm; opt; memory; opt # mapping to internal cell library techmap; opt -- cgit v1.2.3 From 7815f81c320a025c5b92677e375c12951dcbd14b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 16:09:06 +0200 Subject: Added "synth" command --- README | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'README') diff --git a/README b/README index 7e8a42a86..d7f5aaa4b 100644 --- a/README +++ b/README @@ -199,6 +199,19 @@ Various more complex liberty files (for testing) can be found here: ../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib ../cadence/lib/ami05/signalstorm/osu05_stdcells.lib +The command "synth" provides a good default synthesis script (see "help synth"). +If possible a synthesis script should borrow from "synth". For example: + + # the high-level stuff + hierarchy + synth -run coarse + + # mapping to internal cells + techmap; opt -fast + dfflibmap -liberty mycells.lib + abc -liberty mycells.lib + clean + Yosys is under construction. A more detailed documentation will follow. @@ -351,12 +364,7 @@ from SystemVerilog: Roadmap / Large-scale TODOs =========================== -- Verification and Regression Tests - - VlogHammer: http://www.clifford.at/yosys/vloghammer.html - - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - - Technology mapping for real-world applications - - Rewrite current techmap.v rules (modular and clean) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - Implement SAT-based formal equivialence checker @@ -382,7 +390,4 @@ Other Unsorted TODOs - Add brief source code documentation to most passes and kernel code - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - - Add more commands for changing the design (delete, add, modify objects) - - Add full support for $lut cell type (const evaluation, sat solving, etc.) - - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) -- cgit v1.2.3