From b5a3419ac2c6f367b90f062c4e2252029910cdb9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 4 Aug 2014 15:19:24 +0200
Subject: Added support for non-standard "module mod_name(...);" syntax

---
 README | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'README')

diff --git a/README b/README
index 1e0ade91c..63d692297 100644
--- a/README
+++ b/README
@@ -276,6 +276,11 @@ Verilog Attributes and non-standard features
   for everything that comes after the {* ... *} statement. (Reset
   by adding an empty {* *} statement.)
 
+- Modules can be declared with "module mod_name(...);" (with three dots
+  instead of a list of moudle ports). With this syntax it is sufficient
+  to simply declare a module port as 'input' or 'output' in the module
+  body.
+
 - Sized constants (the syntax <size>'s?[bodh]<value>) support constant
   expressions as <size>. If the expresion is not a simple identifier, it
   must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
-- 
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