From a038787c9b51e92440cac3a38801c08f66dbb3af Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Feb 2015 18:52:54 +0100 Subject: Added onehot attribute --- README | 3 +++ 1 file changed, 3 insertions(+) (limited to 'README') diff --git a/README b/README index 476e5ce54..fbd92db36 100644 --- a/README +++ b/README @@ -268,6 +268,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. +- The "onehot" attribute on wires mark them as onehot state register. This + is used for example for memory port sharing and set by the fsm_map pass. + - The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis -- cgit v1.2.3