From 96e7abad48c942452f247267f219d38be902f804 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2013 16:16:06 +0200 Subject: Added iopadmap pass --- README | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index df504ad24..cf5fbdb13 100644 --- a/README +++ b/README @@ -232,7 +232,8 @@ Verilog Attributes and non-standard features - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead - all not explicitly assigned values default to x-bits. + all not explicitly assigned values default to x-bits. This does + not affect clocked storage elements such as flip-flops. - The "nosync" attribute on registers prohibits the generation of a storage element. The register itself will always have all bits set @@ -246,6 +247,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The verilog backend also does not output placeholder modules on default. +- The "keep" attribute on cells is used to mark cells that should never be + removed by the optimizer. This is used for example for cells that have + hidden connections that are not part of the netlist, such as IO pads. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset -- cgit v1.2.3