From 7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Feb 2015 11:21:12 +0100 Subject: Added "read_verilog -nomeminit" and "nomeminit" attribute --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 4ef430938..9fe43ec98 100644 --- a/README +++ b/README @@ -257,6 +257,11 @@ Verilog Attributes and non-standard features - The "mem2reg" attribute on modules or arrays forces the early conversion of arrays to separate registers. +- The "nomeminit" attribute on modules or arrays prohibits the + creation of initialized memories. This effectively puts "mem2reg" + on all memories that are written to in an "initial" block and + are not ROMs. + - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. This does -- cgit v1.2.3