From 295e352ba6aa1bd71431abc21a8f93735968cae6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Nov 2013 15:01:12 +0100 Subject: Renamed "placeholder" to "blackbox" --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index 29e99611d..cc451b2b9 100644 --- a/README +++ b/README @@ -248,11 +248,11 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. -- The "placeholder" attribute on modules is used to mark empty stub modules +- The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis passes to identify input and output ports of cells. The verilog backend - also does not output placeholder modules on default. + also does not output blackbox modules on default. - The "keep" attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that -- cgit v1.2.3