From f66792c43afeacdcceedde83785471e51ee12593 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Apr 2019 08:58:34 -0700 Subject: Fix spelling --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 46bed4242..7b4477053 100644 --- a/README.md +++ b/README.md @@ -370,7 +370,7 @@ Verilog Attributes and non-standard features - When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The - tipple double quotes are removed from the macro body. For example: + triple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; -- cgit v1.2.3 From c6156f3118f327986d801fb48e50b94b7ea9e4b6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Apr 2019 09:01:10 -0700 Subject: Format some names using inline code --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 7b4477053..913777f2e 100644 --- a/README.md +++ b/README.md @@ -457,7 +457,7 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input ($ff cells). The same can be achieved by using + explicit clock input (``$ff`` cells). The same can be achieved by using ``@(posedge )`` or ``@(negedge )`` when ```` is marked with the ``(* gclk *)`` Verilog attribute. @@ -470,7 +470,7 @@ from SystemVerilog: - The ``assert`` statement from SystemVerilog is supported in its most basic form. In module context: ``assert property ();`` and within an - always block: ``assert();``. It is transformed to a $assert cell. + always block: ``assert();``. It is transformed to an ``$assert`` cell. - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are also supported. The same limitations as with the ``assert`` statement apply. -- cgit v1.2.3 From 67005633e246e47683b11e13f08afb788bc9de02 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 23:01:38 +0200 Subject: Add specify support to README Signed-off-by: Clifford Wolf --- README.md | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 913777f2e..d21d60c97 100644 --- a/README.md +++ b/README.md @@ -424,6 +424,11 @@ Verilog Attributes and non-standard features in an unconditional context (only if/case statements on parameters and constant values). The intended use for this is synthesis-time DRC. +- There is limited support for converting specify .. endspecify statements to + special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in + blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this + functionality. (By default specify .. endspecify blocks are ignored.) + Non-standard or SystemVerilog features for formal verification ============================================================== -- cgit v1.2.3 From e2fb8ebe86f49523168c413c734ce4690d740351 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 08:01:39 +0200 Subject: Update README Signed-off-by: Clifford Wolf --- README.md | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index d21d60c97..195329a37 100644 --- a/README.md +++ b/README.md @@ -259,11 +259,7 @@ for them: - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types -- The ``config`` keyword and library map files - -- The ``disable``, ``primitive`` and ``specify`` statements - -- Latched logic (is synthesized as logic with feedback loops) +- The ``config`` and ``disable`` keywords and library map files Verilog Attributes and non-standard features -- cgit v1.2.3 From 05a5027db87cd4e5f88a24d0e4c5c9eb77225a5d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 9 May 2019 15:31:40 +0200 Subject: Add $stop to documentation Signed-off-by: Clifford Wolf --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 195329a37..efb74ef4e 100644 --- a/README.md +++ b/README.md @@ -416,9 +416,10 @@ Verilog Attributes and non-standard features expressions as . If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` -- The system tasks ``$finish`` and ``$display`` are supported in initial blocks - in an unconditional context (only if/case statements on parameters - and constant values). The intended use for this is synthesis-time DRC. +- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in + initial blocks in an unconditional context (only if/case statements on + expressions over parameters and constant values are allowed). The intended + use for this is synthesis-time DRC. - There is limited support for converting specify .. endspecify statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in -- cgit v1.2.3 From 7f11a732102c9e5c32871de9aad2de95b20d988f Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 27 May 2019 18:07:12 +0200 Subject: update README.md with wand/wor information --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index efb74ef4e..73124898d 100644 --- a/README.md +++ b/README.md @@ -138,7 +138,7 @@ writing the design to the console in Yosys's internal format: yosys> write_ilang -elaborate design hierarchy: +elaborate design hierarchy and convert wand/wor nets to logic: yosys> hierarchy @@ -257,7 +257,7 @@ for them: - Non-synthesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 -- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types +- The ``tri``, ``triand`` and ``trior`` net types - The ``config`` and ``disable`` keywords and library map files -- cgit v1.2.3 From ba2185ead89fdb6afeec6043ab18f2e045d80247 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 28 May 2019 16:43:25 +0200 Subject: Refactor hierarchy wand/wor handling Signed-off-by: Clifford Wolf --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 73124898d..19306cda3 100644 --- a/README.md +++ b/README.md @@ -138,7 +138,7 @@ writing the design to the console in Yosys's internal format: yosys> write_ilang -elaborate design hierarchy and convert wand/wor nets to logic: +elaborate design hierarchy: yosys> hierarchy -- cgit v1.2.3 From c66d644b66f13d5cc54c78051bf97c0143d9940e Mon Sep 17 00:00:00 2001 From: Tux3 Date: Tue, 4 Jun 2019 10:45:41 +0200 Subject: README.md: Missing formatting for --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 19306cda3..94ea9538f 100644 --- a/README.md +++ b/README.md @@ -413,7 +413,7 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``'s?[bodh]``) support constant - expressions as . If the expression is not a simple identifier, it + expressions as ````. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in -- cgit v1.2.3