From 4b6c0e331d0ef4188f8fa2443f8f7999231af052 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 May 2018 14:19:05 +0200 Subject: Remove mercurial from build instructions Signed-off-by: Clifford Wolf --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index d5184bd7d..704948e2d 100644 --- a/README.md +++ b/README.md @@ -52,19 +52,19 @@ For example on Ubuntu Linux 16.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ - libreadline-dev gawk tcl-dev libffi-dev git mercurial \ + libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle $ sudo port install bison flex readline gawk libffi \ - git mercurial graphviz pkgconfig python36 + git graphviz pkgconfig python36 On FreeBSD use the following command to install all prerequisites: # pkg install bison flex readline gawk libffi\ - git mercurial graphviz pkgconfig python3 python36 tcl-wrapper + git graphviz pkgconfig python3 python36 tcl-wrapper On FreeBSD system use gmake instead of make. To run tests use: % MAKE=gmake CC=cc gmake test -- cgit v1.2.3 From 4372cf690d829755279a6a5778023e5e0a4493b2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 13:25:42 +0200 Subject: Add (* gclk *) attribute support Signed-off-by: Clifford Wolf --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 704948e2d..c02691d94 100644 --- a/README.md +++ b/README.md @@ -418,7 +418,9 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input ($ff cells). + explicit clock input ($ff cells). The same can be achieved by using + ``@(posedge )`` or ``@(negedge )`` when ```` + is marked with the ``(* gclk *)`` Verilog attribute. Supported features from SystemVerilog -- cgit v1.2.3