From 6cdea425b81fcfe1eec20cbfc4c4e27d46cb641d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 24 Nov 2019 16:05:45 +0100 Subject: clkbufmap: Add support for inverters in clock path. --- README.md | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index e46971526..1ce5d47ea 100644 --- a/README.md +++ b/README.md @@ -343,6 +343,13 @@ Verilog Attributes and non-standard features - The ``clkbuf_sink`` attribute can be set on an input port of a module to request clock buffer insertion by the ``clkbufmap`` pass. +- The ``clkbuf_inv`` attribute can be set on an output port of a module + with the value set to the name of an input port of that module. When + the ``clkbufmap`` would otherwise insert a clock buffer on this output, + it will instead try inserting the clock buffer on the input port (this + is used to implement clock inverter cells that clock buffer insertion + will "see through"). + - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent automatic clock buffer insertion by ``clkbufmap``. This behaviour can be overridden by providing a custom selection to ``clkbufmap``. -- cgit v1.2.3