From d26c512d7ef5369f26436540efee40201e480f7f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 16 Aug 2019 16:07:29 -0700 Subject: Add doc for abc_* attributes --- README.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index d9989eb29..5b30f6bae 100644 --- a/README.md +++ b/README.md @@ -405,6 +405,22 @@ Verilog Attributes and non-standard features blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default specify .. endspecify blocks are ignored.) +- The module attribute ``abc_box_id`` specifies a positive integer linking a + blackbox or whitebox definition to a corresponding entry in a `abc9` + box-file. + +- The port attribute ``abc_scc_break`` indicates a module input port that will + be treated as a primary output during `abc9` techmapping. Doing so eliminates + the possibility of a strongly-connected component (i.e. a combinatorial loop) + existing. Typically, this is specified for sequential inputs on otherwise + combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` + port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths + as a combinatorial loop. + +- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark + the carry-in and carry-out ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. + Non-standard or SystemVerilog features for formal verification ============================================================== -- cgit v1.2.3 From c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:59:57 -0700 Subject: Update doc --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 5b30f6bae..fd4d4beb5 100644 --- a/README.md +++ b/README.md @@ -417,9 +417,10 @@ Verilog Attributes and non-standard features port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths as a combinatorial loop. -- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark - the carry-in and carry-out ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. +- The port attribute ``abc_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect its most significant bit. Non-standard or SystemVerilog features for formal verification -- cgit v1.2.3 From 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 10:00:53 -0700 Subject: Clarify with 'only' --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index fd4d4beb5..56f428548 100644 --- a/README.md +++ b/README.md @@ -420,7 +420,7 @@ Verilog Attributes and non-standard features - The port attribute ``abc_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect its most significant bit. + onto a bus port will affect only its most significant bit. Non-standard or SystemVerilog features for formal verification -- cgit v1.2.3