From c52db44f9ab19194dbdefd35bd697ab99650f510 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 12:13:52 -0700 Subject: Group abc_* attribute doc with other attributes --- README.md | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 38ca77862..95dc01aa8 100644 --- a/README.md +++ b/README.md @@ -347,6 +347,23 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. +- The module attribute ``abc_box_id`` specifies a positive integer linking a + blackbox or whitebox definition to a corresponding entry in a `abc9` + box-file. + +- The port attribute ``abc_scc_break`` indicates a module input port that will + be treated as a primary output during `abc9` techmapping. Doing so eliminates + the possibility of a strongly-connected component (i.e. a combinatorial loop) + existing. Typically, this is specified for sequential inputs on otherwise + combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` + port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths + as a combinatorial loop. + +- The port attribute ``abc_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect only its most significant bit. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset @@ -423,23 +440,6 @@ Verilog Attributes and non-standard features blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default specify .. endspecify blocks are ignored.) -- The module attribute ``abc_box_id`` specifies a positive integer linking a - blackbox or whitebox definition to a corresponding entry in a `abc9` - box-file. - -- The port attribute ``abc_scc_break`` indicates a module input port that will - be treated as a primary output during `abc9` techmapping. Doing so eliminates - the possibility of a strongly-connected component (i.e. a combinatorial loop) - existing. Typically, this is specified for sequential inputs on otherwise - combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` - port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths - as a combinatorial loop. - -- The port attribute ``abc_carry`` marks the carry-in (if an input port) and - carry-out (if output port) ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect only its most significant bit. - Non-standard or SystemVerilog features for formal verification ============================================================== -- cgit v1.2.3 From 9c4e1c6a8fc47f44011f1f75e9493a1bc2de520d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 10:27:07 -0700 Subject: Format `-pwires` --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 38ca77862..0195248a0 100644 --- a/README.md +++ b/README.md @@ -330,7 +330,7 @@ Verilog Attributes and non-standard features - The ``parameter`` and ``localparam`` attributes are used to mark wires that represent module parameters or localparams (when the HDL front-end - is run in -pwires mode). + is run in ``-pwires`` mode). - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` -- cgit v1.2.3