From 2d5d82e2b6f7d369c0d41b499646a8719ff0bc20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 13 Aug 2019 21:47:27 +0200 Subject: README updates --- README.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index d9989eb29..767a0fb61 100644 --- a/README.md +++ b/README.md @@ -329,6 +329,20 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in -pwires mode). +- The ``clkbuf_inhibit`` attribute can be set on a wire to prevent + automatic clock buffer insertion by ``clkbufmap``. + +- The ``clkbuf_sink`` attribute can be set on an input port of a blackbox + module to request clock buffer insertion by the ``clkbufmap`` pass. + +- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox + module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` + from inserting another clock buffer on a net driven by such output. + +- The ``iopad_external_pin`` attribute on a blacbox module's port marks + it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` + from inserting another pad cell on it. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset -- cgit v1.2.3 From d26c512d7ef5369f26436540efee40201e480f7f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 16 Aug 2019 16:07:29 -0700 Subject: Add doc for abc_* attributes --- README.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index d9989eb29..5b30f6bae 100644 --- a/README.md +++ b/README.md @@ -405,6 +405,22 @@ Verilog Attributes and non-standard features blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default specify .. endspecify blocks are ignored.) +- The module attribute ``abc_box_id`` specifies a positive integer linking a + blackbox or whitebox definition to a corresponding entry in a `abc9` + box-file. + +- The port attribute ``abc_scc_break`` indicates a module input port that will + be treated as a primary output during `abc9` techmapping. Doing so eliminates + the possibility of a strongly-connected component (i.e. a combinatorial loop) + existing. Typically, this is specified for sequential inputs on otherwise + combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` + port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths + as a combinatorial loop. + +- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark + the carry-in and carry-out ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. + Non-standard or SystemVerilog features for formal verification ============================================================== -- cgit v1.2.3 From c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:59:57 -0700 Subject: Update doc --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 5b30f6bae..fd4d4beb5 100644 --- a/README.md +++ b/README.md @@ -417,9 +417,10 @@ Verilog Attributes and non-standard features port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths as a combinatorial loop. -- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark - the carry-in and carry-out ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. +- The port attribute ``abc_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect its most significant bit. Non-standard or SystemVerilog features for formal verification -- cgit v1.2.3 From 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 10:00:53 -0700 Subject: Clarify with 'only' --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index fd4d4beb5..56f428548 100644 --- a/README.md +++ b/README.md @@ -420,7 +420,7 @@ Verilog Attributes and non-standard features - The port attribute ``abc_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect its most significant bit. + onto a bus port will affect only its most significant bit. Non-standard or SystemVerilog features for formal verification -- cgit v1.2.3 From e9f3eb97607bc49b6bb77229f1fad9796aea1483 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 22 Aug 2019 18:43:16 +0200 Subject: Bump year in copyright notice Signed-off-by: Clifford Wolf --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 56f428548..a31bd6c37 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ ``` yosys -- Yosys Open SYnthesis Suite -Copyright (C) 2012 - 2018 Clifford Wolf +Copyright (C) 2012 - 2019 Clifford Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above -- cgit v1.2.3 From c618ae43b9e8121690c2842622074a95a12c9fe5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 23 Aug 2019 10:37:50 +0200 Subject: Make macOS depenency clear --- README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index a31bd6c37..606c4942e 100644 --- a/README.md +++ b/README.md @@ -69,11 +69,14 @@ prerequisites for building yosys: graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev -Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: +Similarily, on Mac OS X Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle + +or MacPorts: + $ sudo port install bison flex readline gawk libffi \ - git graphviz pkgconfig python36 boost zlib + git graphviz pkgconfig python36 boost zlib tcl On FreeBSD use the following command to install all prerequisites: -- cgit v1.2.3 From 4c0404ae024e9595934e738a3e8f52be9c22d090 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 10:24:59 -0700 Subject: Mention clkbuf_inhibit can be overridden --- README.md | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 00b631237..38ca77862 100644 --- a/README.md +++ b/README.md @@ -332,17 +332,18 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in -pwires mode). -- The ``clkbuf_inhibit`` attribute can be set on a wire to prevent - automatic clock buffer insertion by ``clkbufmap``. - -- The ``clkbuf_sink`` attribute can be set on an input port of a blackbox - module to request clock buffer insertion by the ``clkbufmap`` pass. - - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` from inserting another clock buffer on a net driven by such output. -- The ``iopad_external_pin`` attribute on a blacbox module's port marks +- The ``clkbuf_sink`` attribute can be set on an input port of a module to + request clock buffer insertion by the ``clkbufmap`` pass. + +- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent + automatic clock buffer insertion by ``clkbufmap``. This behaviour can be + overridden by providing a custom selection to ``clkbufmap``. + +- The ``iopad_external_pin`` attribute on a blackbox module's port marks it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- cgit v1.2.3