From 7b3fe404ab30767a8b65f61fa2a6eebbe9019641 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Fri, 31 Jan 2020 18:20:22 -0300 Subject: $readmem[hb] file inclusion is now relative to the Verilog file Signed-off-by: Rodrigo Alejandro Melo --- CHANGELOG | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 481ba266e..4abfeec06 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -53,12 +53,13 @@ Yosys 0.9 .. Yosys 0.9-dev - Added support for flip-flops with synchronous reset to synth_xilinx - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - - Added checking of SystemVerilog always block types (always_comb, + - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - Added "abc9 -dff" - Added "synth_xilinx -dff" + - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file Yosys 0.8 .. Yosys 0.9 ---------------------- -- cgit v1.2.3