From ea9cc0309245c8d1af5d34b836238f197d34e332 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg <azonenberg@drawersteak.com> Date: Mon, 28 Mar 2016 22:49:46 -0700 Subject: Added GP_SYSRESET block --- techlibs/greenpak4/cells_sim.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6b5100f75..e22bb80cd 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -104,3 +104,10 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); //more complex hard IP blocks are not supported for simulation yet endmodule + +module GP_SYSRESET(input RST); + parameter RESET_MODE = "RISING"; + + //cannot simulate whole system reset + +endmodule -- cgit v1.2.3 From 75f0030458a6c5e37238e2437ea469ba9dfd389b Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg <azonenberg@drawersteak.com> Date: Mon, 28 Mar 2016 23:16:43 -0700 Subject: Added keep constraint to GP_SYSRESET cell --- techlibs/greenpak4/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index e22bb80cd..3acea01d2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -105,6 +105,8 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); endmodule +//keep constraint needed to prevent optimization since we have no outputs +(* keep *) module GP_SYSRESET(input RST); parameter RESET_MODE = "RISING"; -- cgit v1.2.3