From 436c96e2fba0d7f73adb0ebb2b69821fe1dfc58c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 23:29:14 -0800
Subject: Revert "Get rid of holes_mode"

This reverts commit 7997e2a90fd37886241b7eb657408177ef7f6fa7.
---
 backends/aiger/xaiger.cc | 105 +++++++++++++++++++++++++++++++----------------
 1 file changed, 70 insertions(+), 35 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 277017dfd..e7d767721 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -78,7 +78,7 @@ struct XAigerWriter
 	Module *module;
 	SigMap sigmap;
 
-	pool<SigBit> input_bits, output_bits;
+	pool<SigBit> input_bits, output_bits, external_bits;
 	dict<SigBit, SigBit> not_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	vector<SigBit> ci_bits, co_bits;
@@ -136,7 +136,7 @@ struct XAigerWriter
 		return a;
 	}
 
-	XAigerWriter(Module *module) : module(module), sigmap(module)
+	XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -166,7 +166,9 @@ struct XAigerWriter
 				if (bit.wire == nullptr) {
 					if (wire->port_output) {
 						aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
-						output_bits.insert(wirebit);
+						if (holes_mode)
+							output_bits.insert(wirebit);
+						//external_bits.insert(wirebit);
 					}
 					continue;
 				}
@@ -180,7 +182,10 @@ struct XAigerWriter
 				if (wire->port_output) {
 					if (bit != wirebit)
 						alias_map[wirebit] = bit;
-					output_bits.insert(wirebit);
+					if (holes_mode)
+						output_bits.insert(wirebit);
+					else
+						external_bits.insert(wirebit);
 				}
 
 				if (wire->port_input && wire->port_output)
@@ -202,9 +207,11 @@ struct XAigerWriter
 				unused_bits.erase(A);
 				undriven_bits.erase(Y);
 				not_map[Y] = A;
-				toposort.node(cell->name);
-				bit_users[A].insert(cell->name);
-				bit_drivers[Y].insert(cell->name);
+				if (!holes_mode) {
+					toposort.node(cell->name);
+					bit_users[A].insert(cell->name);
+					bit_drivers[Y].insert(cell->name);
+				}
 				continue;
 			}
 
@@ -217,13 +224,17 @@ struct XAigerWriter
 				unused_bits.erase(B);
 				undriven_bits.erase(Y);
 				and_map[Y] = make_pair(A, B);
-				toposort.node(cell->name);
-				bit_users[A].insert(cell->name);
-				bit_users[B].insert(cell->name);
-				bit_drivers[Y].insert(cell->name);
+				if (!holes_mode) {
+					toposort.node(cell->name);
+					bit_users[A].insert(cell->name);
+					bit_users[B].insert(cell->name);
+					bit_drivers[Y].insert(cell->name);
+				}
 				continue;
 			}
 
+			log_assert(!holes_mode);
+
 			if (cell->type == "$__ABC9_FF_")
 			{
 				SigBit D = sigmap(cell->getPort("\\D").as_bit());
@@ -287,7 +298,7 @@ struct XAigerWriter
 				if (!is_input && !is_output)
 					log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
-				if (is_input)
+				if (is_input) {
 					for (auto b : c.second) {
 						Wire *w = b.wire;
 						if (!w) continue;
@@ -295,19 +306,13 @@ struct XAigerWriter
 							SigBit I = sigmap(b);
 							if (I != b)
 								alias_map[b] = I;
-							output_bits.insert(b);
+							if (holes_mode)
+								output_bits.insert(b);
+							else
+								external_bits.insert(b);
 						}
 					}
-
-				if (is_output)
-					for (auto b : c.second) {
-						Wire *w = b.wire;
-						if (!w) continue;
-						SigBit O = sigmap(b);
-						if (O != b)
-							alias_map[O] = b;
-						input_bits.insert(O);
-					}
+				}
 			}
 
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
@@ -490,27 +495,57 @@ struct XAigerWriter
 			// TODO: Free memory from toposort, bit_drivers, bit_users
 		}
 
+		if (!holes_mode)
+			for (auto cell : module->cells())
+				if (!module->selected(cell))
+					for (auto &conn : cell->connections())
+						if (cell->input(conn.first))
+							for (auto wirebit : conn.second)
+								if (sigmap(wirebit).wire)
+									external_bits.insert(wirebit);
+
+		// For all bits consumed outside of the selected cells,
+		//   but driven from a selected cell, then add it as
+		//   a primary output
+		for (auto wirebit : external_bits) {
+			SigBit bit = sigmap(wirebit);
+			if (!bit.wire)
+				continue;
+			if (!undriven_bits.count(bit)) {
+				if (bit != wirebit)
+					alias_map[wirebit] = bit;
+				output_bits.insert(wirebit);
+			}
+		}
+
 		for (auto bit : input_bits)
-			undriven_bits.erase(bit);
+			undriven_bits.erase(sigmap(bit));
 		for (auto bit : output_bits)
 			unused_bits.erase(sigmap(bit));
 		for (auto bit : unused_bits)
 			undriven_bits.erase(bit);
-		if (!undriven_bits.empty()) {
+
+		// Make all undriven bits a primary input
+		if (!holes_mode)
 			for (auto bit : undriven_bits) {
-				log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
 				input_bits.insert(bit);
+				undriven_bits.erase(bit);
 			}
-			log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
+
+		if (holes_mode) {
+			struct sort_by_port_id {
+				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+					return a.wire->port_id < b.wire->port_id;
+				}
+			};
+			input_bits.sort(sort_by_port_id());
+			output_bits.sort(sort_by_port_id());
+		}
+		else {
+			input_bits.sort();
+			output_bits.sort();
 		}
 
-		struct sort_by_port_id {
-			bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-				return a.wire->port_id < b.wire->port_id;
-			}
-		};
-		input_bits.sort(sort_by_port_id());
-		output_bits.sort(sort_by_port_id());
 		not_map.sort();
 		and_map.sort();
 
@@ -842,7 +877,7 @@ struct XAigerWriter
 				Pass::call(holes_design, "opt -purge");
 
 				std::stringstream a_buffer;
-				XAigerWriter writer(holes_module);
+				XAigerWriter writer(holes_module, true /* holes_mode */);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/);
 				delete holes_design;
 
-- 
cgit v1.2.3


From 3798fa3bead6b944ebdee892c9bf5231559766f1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 09:59:17 -0800
Subject: Retry getting rid of write_xaiger's holes_mode

---
 backends/aiger/xaiger.cc | 122 ++++++++++++++++-------------------------------
 1 file changed, 41 insertions(+), 81 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e7d767721..40cf72548 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -136,11 +136,10 @@ struct XAigerWriter
 		return a;
 	}
 
-	XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
+	XAigerWriter(Module *module) : module(module), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
-		pool<SigBit> inout_bits;
 
 		// promote public wires
 		for (auto wire : module->wires())
@@ -157,7 +156,12 @@ struct XAigerWriter
 			if (wire->get_bool_attribute(ID::keep))
 				sigmap.add(wire);
 
-		for (auto wire : module->wires())
+		// First, collect all the ports in port_id order
+		//   since module->wires() could be sorted
+		//   alphabetically
+		for (auto port : module->ports) {
+			auto wire = module->wire(port);
+			log_assert(wire);
 			for (int i = 0; i < GetSize(wire); i++)
 			{
 				SigBit wirebit(wire, i);
@@ -166,30 +170,32 @@ struct XAigerWriter
 				if (bit.wire == nullptr) {
 					if (wire->port_output) {
 						aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
-						if (holes_mode)
-							output_bits.insert(wirebit);
-						//external_bits.insert(wirebit);
+						output_bits.insert(wirebit);
 					}
 					continue;
 				}
 
-				undriven_bits.insert(bit);
-				unused_bits.insert(bit);
-
 				if (wire->port_input)
 					input_bits.insert(bit);
 
 				if (wire->port_output) {
 					if (bit != wirebit)
 						alias_map[wirebit] = bit;
-					if (holes_mode)
-						output_bits.insert(wirebit);
-					else
-						external_bits.insert(wirebit);
+					output_bits.insert(wirebit);
 				}
+			}
+		}
+
+		for (auto wire : module->wires())
+			for (int i = 0; i < GetSize(wire); i++)
+			{
+				SigBit wirebit(wire, i);
+				SigBit bit = sigmap(wirebit);
 
-				if (wire->port_input && wire->port_output)
-					inout_bits.insert(wirebit);
+				if (bit.wire) {
+					undriven_bits.insert(bit);
+					unused_bits.insert(bit);
+				}
 			}
 
 		// TODO: Speed up toposort -- ultimately we care about
@@ -207,11 +213,9 @@ struct XAigerWriter
 				unused_bits.erase(A);
 				undriven_bits.erase(Y);
 				not_map[Y] = A;
-				if (!holes_mode) {
-					toposort.node(cell->name);
-					bit_users[A].insert(cell->name);
-					bit_drivers[Y].insert(cell->name);
-				}
+				toposort.node(cell->name);
+				bit_users[A].insert(cell->name);
+				bit_drivers[Y].insert(cell->name);
 				continue;
 			}
 
@@ -224,17 +228,13 @@ struct XAigerWriter
 				unused_bits.erase(B);
 				undriven_bits.erase(Y);
 				and_map[Y] = make_pair(A, B);
-				if (!holes_mode) {
-					toposort.node(cell->name);
-					bit_users[A].insert(cell->name);
-					bit_users[B].insert(cell->name);
-					bit_drivers[Y].insert(cell->name);
-				}
+				toposort.node(cell->name);
+				bit_users[A].insert(cell->name);
+				bit_users[B].insert(cell->name);
+				bit_drivers[Y].insert(cell->name);
 				continue;
 			}
 
-			log_assert(!holes_mode);
-
 			if (cell->type == "$__ABC9_FF_")
 			{
 				SigBit D = sigmap(cell->getPort("\\D").as_bit());
@@ -298,7 +298,7 @@ struct XAigerWriter
 				if (!is_input && !is_output)
 					log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
-				if (is_input) {
+				if (is_input)
 					for (auto b : c.second) {
 						Wire *w = b.wire;
 						if (!w) continue;
@@ -306,13 +306,9 @@ struct XAigerWriter
 							SigBit I = sigmap(b);
 							if (I != b)
 								alias_map[b] = I;
-							if (holes_mode)
-								output_bits.insert(b);
-							else
-								external_bits.insert(b);
+							output_bits.insert(b);
 						}
 					}
-				}
 			}
 
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
@@ -495,29 +491,6 @@ struct XAigerWriter
 			// TODO: Free memory from toposort, bit_drivers, bit_users
 		}
 
-		if (!holes_mode)
-			for (auto cell : module->cells())
-				if (!module->selected(cell))
-					for (auto &conn : cell->connections())
-						if (cell->input(conn.first))
-							for (auto wirebit : conn.second)
-								if (sigmap(wirebit).wire)
-									external_bits.insert(wirebit);
-
-		// For all bits consumed outside of the selected cells,
-		//   but driven from a selected cell, then add it as
-		//   a primary output
-		for (auto wirebit : external_bits) {
-			SigBit bit = sigmap(wirebit);
-			if (!bit.wire)
-				continue;
-			if (!undriven_bits.count(bit)) {
-				if (bit != wirebit)
-					alias_map[wirebit] = bit;
-				output_bits.insert(wirebit);
-			}
-		}
-
 		for (auto bit : input_bits)
 			undriven_bits.erase(sigmap(bit));
 		for (auto bit : output_bits)
@@ -526,33 +499,18 @@ struct XAigerWriter
 			undriven_bits.erase(bit);
 
 		// Make all undriven bits a primary input
-		if (!holes_mode)
-			for (auto bit : undriven_bits) {
-				input_bits.insert(bit);
-				undriven_bits.erase(bit);
-			}
-
-		if (holes_mode) {
-			struct sort_by_port_id {
-				bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-					return a.wire->port_id < b.wire->port_id;
-				}
-			};
-			input_bits.sort(sort_by_port_id());
-			output_bits.sort(sort_by_port_id());
-		}
-		else {
-			input_bits.sort();
-			output_bits.sort();
+		for (auto bit : undriven_bits) {
+			input_bits.insert(bit);
+			undriven_bits.erase(bit);
 		}
 
-		not_map.sort();
-		and_map.sort();
-
 		aig_map[State::S0] = 0;
 		aig_map[State::S1] = 1;
 
-		for (auto bit : input_bits) {
+		// pool<> iterates in LIFO order...
+		for (int i = input_bits.size()-1; i >= 0; i--) {
+			const auto &bit = *input_bits.element(i);
+			log_dump(bit, i);
 			aig_m++, aig_i++;
 			log_assert(!aig_map.count(bit));
 			aig_map[bit] = 2*aig_m;
@@ -578,7 +536,9 @@ struct XAigerWriter
 			aig_outputs.push_back(bit2aig(bit));
 		}
 
-		for (auto bit : output_bits) {
+		// pool<> iterates in LIFO order...
+		for (int i = output_bits.size()-1; i >= 0; i--) {
+			const auto &bit = *output_bits.element(i);
 			ordered_outputs[bit] = aig_o++;
 			aig_outputs.push_back(bit2aig(bit));
 		}
@@ -877,7 +837,7 @@ struct XAigerWriter
 				Pass::call(holes_design, "opt -purge");
 
 				std::stringstream a_buffer;
-				XAigerWriter writer(holes_module, true /* holes_mode */);
+				XAigerWriter writer(holes_module);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/);
 				delete holes_design;
 
-- 
cgit v1.2.3


From 134e70e8e7798dd1e841b8deac2165c9f334ba09 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 10:21:11 -0800
Subject: write_xaiger: be more precise with ff_bits, remove ff_aig_map

---
 backends/aiger/xaiger.cc | 40 +++++++++++++++++++---------------------
 1 file changed, 19 insertions(+), 21 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 40cf72548..650ceba7a 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -82,7 +82,7 @@ struct XAigerWriter
 	dict<SigBit, SigBit> not_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	vector<SigBit> ci_bits, co_bits;
-	dict<SigBit, std::pair<int,int>> ff_bits;
+	dict<SigBit, std::tuple<SigBit,int,int>> ff_bits;
 	dict<SigBit, float> arrival_times;
 
 	vector<pair<int, int>> aig_gates;
@@ -242,7 +242,7 @@ struct XAigerWriter
 				unused_bits.erase(D);
 				undriven_bits.erase(Q);
 				alias_map[Q] = D;
-				auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, 2)));
+				auto r = ff_bits.insert(std::make_pair(D, std::make_tuple(Q, 0, 2)));
 				log_assert(r.second);
 				continue;
 			}
@@ -348,25 +348,26 @@ struct XAigerWriter
 
 				auto it = cell->attributes.find(ID(abc9_mergeability));
 				log_assert(it != cell->attributes.end());
-				rhs.first = it->second.as_int();
+				std::get<1>(rhs) = it->second.as_int();
 				cell->attributes.erase(it);
 
 				it = cell->attributes.find(ID(abc9_init));
 				log_assert(it != cell->attributes.end());
 				log_assert(GetSize(it->second) == 1);
 				if (it->second[0] == State::S1)
-					rhs.second = 1;
+					std::get<2>(rhs) = 1;
 				else if (it->second[0] == State::S0)
-					rhs.second = 0;
+					std::get<2>(rhs) = 0;
 				else {
 					log_assert(it->second[0] == State::Sx);
-					rhs.second = 0;
+					std::get<2>(rhs) = 0;
 				}
 				cell->attributes.erase(it);
 
+				const SigBit &q = std::get<0>(rhs);
 				auto arrival = r.first->second.second;
 				if (arrival)
-					arrival_times[d] = arrival;
+					arrival_times[q] = arrival;
 			}
 
 			for (auto &it : bit_users)
@@ -510,25 +511,22 @@ struct XAigerWriter
 		// pool<> iterates in LIFO order...
 		for (int i = input_bits.size()-1; i >= 0; i--) {
 			const auto &bit = *input_bits.element(i);
-			log_dump(bit, i);
 			aig_m++, aig_i++;
 			log_assert(!aig_map.count(bit));
 			aig_map[bit] = 2*aig_m;
 		}
 
 		for (const auto &i : ff_bits) {
-			const SigBit &bit = i.first;
+			const SigBit &q = std::get<0>(i.second);
 			aig_m++, aig_i++;
-			log_assert(!aig_map.count(bit));
-			aig_map[bit] = 2*aig_m;
+			log_assert(!aig_map.count(q));
+			aig_map[q] = 2*aig_m;
 		}
 
-		dict<SigBit, int> ff_aig_map;
 		for (auto &bit : ci_bits) {
 			aig_m++, aig_i++;
-			auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
-			if (!r.second)
-				ff_aig_map[bit] = 2*aig_m;
+			log_assert(!aig_map.count(bit));
+			aig_map[bit] = 2*aig_m;
 		}
 
 		for (auto bit : co_bits) {
@@ -544,9 +542,9 @@ struct XAigerWriter
 		}
 
 		for (auto &i : ff_bits) {
-			const SigBit &bit = i.first;
+			const SigBit &d = i.first;
 			aig_o++;
-			aig_outputs.push_back(ff_aig_map.at(bit));
+			aig_outputs.push_back(aig_map.at(d));
 		}
 	}
 
@@ -752,13 +750,13 @@ struct XAigerWriter
 			write_s_buffer(ff_bits.size());
 
 			for (const auto &i : ff_bits) {
-				const SigBit &bit = i.first;
-				int mergeability = i.second.first;
+				const SigBit &q = std::get<0>(i.second);
+				int mergeability = std::get<1>(i.second);
 				log_assert(mergeability > 0);
 				write_r_buffer(mergeability);
-				int init = i.second.second;
+				int init = std::get<2>(i.second);
 				write_s_buffer(init);
-				write_i_buffer(arrival_times.at(bit, 0));
+				write_i_buffer(arrival_times.at(q, 0));
 				//write_o_buffer(0);
 			}
 
-- 
cgit v1.2.3


From 789211d9b3a6892c72d22a09bf2299075337f9f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 11:13:50 -0800
Subject: Fix incorrect $__ABC9_ASYNC[01] box

---
 techlibs/xilinx/abc9_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 2cabe57d7..a3f9e311e 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -186,7 +186,7 @@ module FDCE (output Q, input C, CE, D, CLR);
                                             //     $__ABC9_ASYNC1 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -204,7 +204,7 @@ module FDCE (output Q, input C, CE, D, CLR);
                                            //     $__ABC9_ASYNC0 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end endgenerate
   $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
 
-- 
cgit v1.2.3


From b4663a987bc1bac3aa4cccab99dc191825902205 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 11:14:11 -0800
Subject: Fix attributes on $__ABC9_ASYNC[01] whitebox

---
 techlibs/xilinx/abc9_model.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index c793396a4..11250123d 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -34,13 +34,13 @@ module \$__ABC9_FF_ (input D, output Q);
 endmodule
 
 // Box to emulate async behaviour of FDC*
-(* abc_box_id = 1000 *)
+(* abc9_box_id = 1000, lib_whitebox *)
 module \$__ABC9_ASYNC0 (input A, S, output Y);
   assign Y = S ? 1'b0 : A;
 endmodule
 
 // Box to emulate async behaviour of FDP*
-(* abc_box_id = 1001 *)
+(* abc9_box_id = 1001, lib_whitebox *)
 module \$__ABC9_ASYNC1 (input A, S, output Y);
   assign Y = S ? 1'b0 : A;
 endmodule
-- 
cgit v1.2.3


From 4cdba00e25d892b90c0ee48716c17dec60e472db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 15:24:02 -0800
Subject: FDCE ports to be alphabetical

---
 techlibs/xilinx/cells_sim.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4d20e1d2c..982ccad72 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -405,10 +405,10 @@ module FDCE (
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   input CE,
-  (* invertible_pin = "IS_D_INVERTED" *)
-  input D,
   (* invertible_pin = "IS_CLR_INVERTED" *)
-  input CLR
+  input CLR,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D
 );
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
-- 
cgit v1.2.3


From 6b825c719b5bf6f63d3397cfadf8293b5d14dde6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 15:25:46 -0800
Subject: Update abc9_xc7.box comments

---
 techlibs/xilinx/abc9_xc7.box | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 16606d14e..67523124a 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -1,8 +1,9 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 #                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
 # Average across F7[AB]MUX
 # Inputs: I0 I1 S0
@@ -15,7 +16,7 @@ MUXF7 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-# Box containing MUXF7.[AB] + MUXF8,
+# Box containing MUXF7.[AB] + MUXF8
 #   Necessary to make these an atomic unit so that
 #   ABC cannot optimise just one of the MUXF7 away
 #   and expect to save on its delay
@@ -27,8 +28,8 @@ $__MUXF78 3 1 6 1
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
-#   (NB: carry chain input/output must be last
-#        input/output and the entire bus has been
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
 #        moved there overriding the otherwise
 #        alphabetical ordering)
 CARRY4 4 1 10 8
@@ -53,55 +54,54 @@ $__ABC9_ASYNC0 1000 1 2 1
 $__ABC9_ASYNC1 1001 1 2 1
 0 764
 
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-#                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+# Flop boxes:
+# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+#                   https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exception for \$currQ)
-
-# Inputs: C CE D R \$currQ
+# Inputs: C CE D R $abc9_currQ
 # Outputs: Q
 FDRE 1100 1 5 1
 #0 109 -46 404 0
 0 109 0 404 0 # Clamp -46ps Tsu
 
-# Inputs: C CE D R \$currQ
+# Inputs: C CE D R $abc9_currQ
 # Outputs: Q
 FDRE_1 1101 1 5 1
 #0 109 0 -46 404
 0 109 0 0 404 # Clamp -46ps Tsu
 
-# Inputs: C CE CLR D \$currQ
+# Inputs: C CE CLR D $abc9_currQ
 # Outputs: Q
 FDCE 1102 1 5 1
 #0 109 764 -46 0
 0 109 764 0 0 # Clamp -46ps Tsu
 
-# Inputs: C CE CLR D \$currQ
+# Inputs: C CE CLR D $abc9_currQ
 # Outputs: Q
 FDCE_1 1103 1 5 1
 #0 109 764 -46 0
 0 109 764 0 0 # Clamp -46ps Tsu
 
-# Inputs: C CE D PRE \$currQ
+# Inputs: C CE D PRE $abc9_currQ
 # Outputs: Q
 FDPE 1104 1 5 1
 #0 109 -46 764 0
 0 109 0 764 0 # Clamp -46ps Tsu
 
-# Inputs: C CE D PRE \$currQ
+# Inputs: C CE D PRE $abc9_currQ
 # Outputs: Q
 FDPE_1 1105 1 5 1
 #0 109 -46 764 0
 0 109 0 764 0 # Clamp -46ps Tsu
 
-# Inputs: C CE D S \$currQ
+# Inputs: C CE D S $abc9_currQ
 # Outputs: Q
 FDSE 1106 1 5 1
 #0 109 -46 446 0
 0 109 0 446 0 # Clamp -46ps Tsu
 
-# Inputs: C CE D S \$currQ
+# Inputs: C CE D S $abc9_currQ
 # Outputs: Q
 FDSE_1 1107 1 5 1
 #0 109 -46 446 0
-- 
cgit v1.2.3


From cac7f5d82eb2760bcc248d15315b0d8460c92cb0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 16:12:40 -0800
Subject: Do not re-order carry chain ports, just precompute iteration order

---
 backends/aiger/xaiger.cc | 54 ++++++++++++++++++++++++++++--------------------
 passes/techmap/abc9.cc   | 22 --------------------
 2 files changed, 32 insertions(+), 44 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 650ceba7a..3e40562b7 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -93,6 +93,7 @@ struct XAigerWriter
 	dict<SigBit, int> ordered_outputs;
 
 	vector<Cell*> box_list;
+	dict<IdString, std::vector<IdString>> box_ports;
 
 	int mkgate(int a0, int a1)
 	{
@@ -404,12 +405,34 @@ struct XAigerWriter
 
 				bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
 
+				auto r = box_ports.insert(cell->type);
+				if (r.second) {
+					// Make carry in the last PI, and carry out the last PO
+					//   since ABC requires it this way
+					IdString carry_in, carry_out;
+					for (const auto &port_name : box_module->ports) {
+						auto w = box_module->wire(port_name);
+						log_assert(w);
+						if (w->get_bool_attribute("\\abc9_carry")) {
+							if (w->port_input)
+								carry_in = port_name;
+							if (w->port_output)
+								carry_out = port_name;
+						}
+						else
+							r.first->second.push_back(port_name);
+					}
+					if (carry_in != IdString()) {
+						log_assert(carry_out != IdString());
+						r.first->second.push_back(carry_in);
+						r.first->second.push_back(carry_out);
+					}
+				}
+
 				// Fully pad all unused input connections of this box cell with S0
 				// Fully pad all undriven output connections of this box cell with anonymous wires
-				// NB: Assume box_module->ports are sorted alphabetically
-				//     (as RTLIL::Module::fixup_ports() would do)
-				for (const auto &port_name : box_module->ports) {
-					RTLIL::Wire* w = box_module->wire(port_name);
+				for (auto port_name : r.first->second) {
+					auto w = box_module->wire(port_name);
 					log_assert(w);
 					auto it = cell->connections_.find(port_name);
 					if (w->port_input) {
@@ -424,7 +447,7 @@ struct XAigerWriter
 							cell->setPort(port_name, rhs);
 						}
 
-						for (auto b : rhs.bits()) {
+						for (auto b : rhs) {
 							SigBit I = sigmap(b);
 							if (b == RTLIL::Sx)
 								b = State::S0;
@@ -455,11 +478,10 @@ struct XAigerWriter
 						}
 
 						for (const auto &b : rhs.bits()) {
-							ci_bits.emplace_back(b);
 							SigBit O = sigmap(b);
 							if (O != b)
 								alias_map[O] = b;
-							input_bits.erase(O);
+							ci_bits.emplace_back(b);
 							undriven_bits.erase(O);
 						}
 					}
@@ -653,33 +675,21 @@ struct XAigerWriter
 				if (box_module->has_processes())
 					Pass::call_on_module(module->design, box_module, "proc");
 
-				int box_inputs = 0, box_outputs = 0;
 				auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
 				Cell *holes_cell = r.first->second;
 				if (r.second && box_module->get_bool_attribute("\\whitebox")) {
 					holes_cell = holes_module->addCell(cell->name, cell->type);
 					holes_cell->parameters = cell->parameters;
 					r.first->second = holes_cell;
-
-					// Since Module::derive() will create a new module, there
-					//   is a chance that the ports will be alphabetically ordered
-					//   again, which is a problem when carry-chains are involved.
-					//   Inherit the port ordering from the original module here...
-					//   (and set the port_id below, when iterating through those)
-					log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
-					box_module->ports = orig_box_module->ports;
 				}
 
-				// NB: Assume box_module->ports are sorted alphabetically
-				//     (as RTLIL::Module::fixup_ports() would do)
-				int box_port_id = 1;
-				for (const auto &port_name : box_module->ports) {
+				int box_inputs = 0, box_outputs = 0;
+				for (auto port_name : box_ports.at(cell->type)) {
 					RTLIL::Wire *w = box_module->wire(port_name);
 					log_assert(w);
-					if (r.second)
-						w->port_id = box_port_id++;
 					RTLIL::Wire *holes_wire;
 					RTLIL::SigSpec port_sig;
+
 					if (w->port_input)
 						for (int i = 0; i < GetSize(w); i++) {
 							box_inputs++;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b63a1aa6c..1ae1637bd 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1003,28 +1003,6 @@ struct Abc9Pass : public Pass {
 					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
 				if (!carry_in && carry_out)
 					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-				// Make carry_in the last PI, and carry_out the last PO
-				//   since ABC requires it this way
-				auto &ports = m->ports;
-				for (auto it = ports.begin(); it != ports.end(); ) {
-					RTLIL::Wire* w = m->wire(*it);
-					log_assert(w);
-					if (w == carry_in || w == carry_out) {
-						it = ports.erase(it);
-						continue;
-					}
-					if (w->port_id > carry_in->port_id)
-						--w->port_id;
-					if (w->port_id > carry_out->port_id)
-						--w->port_id;
-					log_assert(w->port_input || w->port_output);
-					log_assert(ports[w->port_id-1] == w->name);
-					++it;
-				}
-				ports.push_back(carry_in->name);
-				carry_in->port_id = ports.size();
-				ports.push_back(carry_out->name);
-				carry_out->port_id = ports.size();
 			}
 		}
 
-- 
cgit v1.2.3


From ccc0a740d254e6895b49037681bc484d6572342d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 16:16:05 -0800
Subject: Add some abc9 dff tests

---
 tests/arch/xilinx/abc9_dff.ys | 55 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 tests/arch/xilinx/abc9_dff.ys

diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
new file mode 100644
index 000000000..6611b4f18
--- /dev/null
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -0,0 +1,55 @@
+read_verilog <<EOT
+module top(input C, D, output [3:0] Q);
+FDRE   fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
+FDSE   fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
+FDCE   fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
+FDPE   fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
+endmodule
+EOT
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-none t:FD*
+
+
+design -reset
+read_verilog <<EOT
+module top(input C, D, output [3:0] Q);
+FDRE   fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE   fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE   fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE   fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+endmodule
+EOT
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-none t:FD*
+
+
+design -reset
+read_verilog <<EOT
+module top(input C, D, output [3:0] Q);
+FDRE_1 fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
+FDSE_1 fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
+FDCE_1 fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
+FDPE_1 fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
+endmodule
+EOT
+
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-none t:FD*
+
+
+design -reset
+read_verilog <<EOT
+module top(input C, D, output [3:0] Q);
+FDRE_1 fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE_1 fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE_1 fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE_1 fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+endmodule
+EOT
+
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-none t:FD*
-- 
cgit v1.2.3


From e5ed8e8e2172c243bcca651eedd81053a5d7f575 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 16:50:22 -0800
Subject: parse_xaiger to reorder ports too

---
 frontends/aiger/aigerparse.cc | 67 +++++++++++++++++--------------------------
 1 file changed, 26 insertions(+), 41 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9cb05dfb3..3d00aee10 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -722,6 +722,7 @@ void AigerReader::post_process()
 {
 	pool<IdString> seen_boxes;
 	pool<IdString> flops;
+	dict<IdString, std::vector<IdString>> box_ports;
 	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
@@ -734,51 +735,35 @@ void AigerReader::post_process()
 				flops.insert(cell->type);
 				is_flop = true;
 			}
-			auto it = box_module->attributes.find("\\abc9_carry");
-			if (it != box_module->attributes.end()) {
-				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-				auto carry_in_out = it->second.decode_string();
-				auto pos = carry_in_out.find(',');
-				if (pos == std::string::npos)
-					log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
-				auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
-				carry_in = box_module->wire(carry_in_name);
-				if (!carry_in || !carry_in->port_input)
-					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
-
-				auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
-				carry_out = box_module->wire(carry_out_name);
-				if (!carry_out || !carry_out->port_output)
-					log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
-
-				auto &ports = box_module->ports;
-				for (auto jt = ports.begin(); jt != ports.end(); ) {
-					RTLIL::Wire* w = box_module->wire(*jt);
-					log_assert(w);
-					if (w == carry_in || w == carry_out) {
-						jt = ports.erase(jt);
-						continue;
-					}
-					if (w->port_id > carry_in->port_id)
-						--w->port_id;
-					if (w->port_id > carry_out->port_id)
-						--w->port_id;
-					log_assert(w->port_input || w->port_output);
-					log_assert(ports[w->port_id-1] == w->name);
-					++jt;
-				}
-				ports.push_back(carry_in->name);
-				carry_in->port_id = ports.size();
-				ports.push_back(carry_out->name);
-				carry_out->port_id = ports.size();
-			}
 		}
 		else
 			is_flop = flops.count(cell->type);
 
-		// NB: Assume box_module->ports are sorted alphabetically
-		//     (as RTLIL::Module::fixup_ports() would do)
-		for (auto port_name : box_module->ports) {
+		auto r = box_ports.insert(cell->type);
+		if (r.second) {
+			// Make carry in the last PI, and carry out the last PO
+			//   since ABC requires it this way
+			IdString carry_in, carry_out;
+			for (const auto &port_name : box_module->ports) {
+				auto w = box_module->wire(port_name);
+				log_assert(w);
+				if (w->get_bool_attribute("\\abc9_carry")) {
+					if (w->port_input)
+						carry_in = port_name;
+					if (w->port_output)
+						carry_out = port_name;
+				}
+				else
+					r.first->second.push_back(port_name);
+			}
+			if (carry_in != IdString()) {
+				log_assert(carry_out != IdString());
+				r.first->second.push_back(carry_in);
+				r.first->second.push_back(carry_out);
+			}
+		}
+
+		for (auto port_name : box_ports.at(cell->type)) {
 			RTLIL::Wire* port = box_module->wire(port_name);
 			log_assert(port);
 			RTLIL::SigSpec rhs;
-- 
cgit v1.2.3


From 96db05aaefd970c819ba1f75b7246c5958527b8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 17:06:03 -0800
Subject: parse_xaiger to not take box_lookup

---
 backends/aiger/xaiger.cc      | 15 ++++++++++++--
 frontends/aiger/aigerparse.cc | 36 +++++++++++++++++----------------
 frontends/aiger/aigerparse.h  |  2 +-
 passes/techmap/abc9.cc        | 47 ++++---------------------------------------
 4 files changed, 37 insertions(+), 63 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3e40562b7..be900f0e7 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -414,14 +414,25 @@ struct XAigerWriter
 						auto w = box_module->wire(port_name);
 						log_assert(w);
 						if (w->get_bool_attribute("\\abc9_carry")) {
-							if (w->port_input)
+							if (w->port_input) {
+								if (carry_in != IdString())
+									log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
 								carry_in = port_name;
-							if (w->port_output)
+							}
+							if (w->port_output) {
+								if (carry_out != IdString())
+									log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
 								carry_out = port_name;
+							}
 						}
 						else
 							r.first->second.push_back(port_name);
 					}
+
+					if (carry_in != IdString() && carry_out == IdString())
+						log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+					if (carry_in == IdString() && carry_out != IdString())
+						log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
 					if (carry_in != IdString()) {
 						log_assert(carry_out != IdString());
 						r.first->second.push_back(carry_in);
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 3d00aee10..f030933ec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -340,7 +340,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
 	return wire;
 }
 
-void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
+void AigerReader::parse_xaiger()
 {
 	std::string header;
 	f >> header;
@@ -382,6 +382,21 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 	if (f.peek() == '\n')
 		f.get();
 
+	dict<int,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		auto it = m->attributes.find(ID(abc9_box_id));
+		if (it == m->attributes.end())
+			continue;
+		if (m->name.begins_with("$paramod"))
+			continue;
+		auto id = it->second.as_int();
+		auto r = box_lookup.insert(std::make_pair(id, m->name));
+		if (!r.second)
+			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+					log_id(m), id, log_id(r.first->second));
+		log_assert(r.second);
+	}
+
 	// Parse footer (symbol table, comments, etc.)
 	std::string s;
 	for (int c = f.get(); c != EOF; c = f.get()) {
@@ -456,7 +471,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
 				uint32_t boxUniqueId = parse_xaiger_literal(f);
 				log_assert(boxUniqueId > 0);
 				uint32_t oldBoxNum = parse_xaiger_literal(f);
-				RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId));
+				RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
 				boxes.emplace_back(cell);
 			}
 		}
@@ -720,25 +735,12 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-	pool<IdString> seen_boxes;
-	pool<IdString> flops;
 	dict<IdString, std::vector<IdString>> box_ports;
 	unsigned ci_count = 0, co_count = 0, flop_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
 		log_assert(box_module);
 
-		bool is_flop = false;
-		if (seen_boxes.insert(cell->type).second) {
-			if (box_module->attributes.count("\\abc9_flop")) {
-				log_assert(flop_count < flopNum);
-				flops.insert(cell->type);
-				is_flop = true;
-			}
-		}
-		else
-			is_flop = flops.count(cell->type);
-
 		auto r = box_ports.insert(cell->type);
 		if (r.second) {
 			// Make carry in the last PI, and carry out the last PO
@@ -788,7 +790,7 @@ void AigerReader::post_process()
 			cell->setPort(port_name, rhs);
 		}
 
-		if (is_flop) {
+		if (box_module->attributes.count("\\abc9_flop")) {
 			log_assert(co_count < outputs.size());
 			Wire *wire = outputs[co_count++];
 			log_assert(wire);
@@ -900,7 +902,7 @@ void AigerReader::post_process()
 					wire->attributes["\\init"] = init;
 			}
 			else if (type == "box") {
-				RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable));
+				RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
 				if (cell) { // ABC could have optimised this box away
 					module->rename(cell, escaped_s);
 					for (const auto &i : cell->connections()) {
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 583c9d0f9..de3c3efbc 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -47,7 +47,7 @@ struct AigerReader
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
     void parse_aiger();
-    void parse_xaiger(const dict<int,IdString> &box_lookup);
+    void parse_xaiger();
     void parse_aiger_ascii();
     void parse_aiger_binary();
     void post_process();
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1ae1637bd..3c53a5223 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -251,7 +251,7 @@ struct abc9_output_filter
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
 		bool cleanup, vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
 		const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
-		std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
+		std::string wire_delay, bool nomfs
 )
 {
 	map_autoidx = autoidx++;
@@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		log_assert(!design->module(ID($__abc9__)));
 		{
 			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-			reader.parse_xaiger(box_lookup);
+			reader.parse_xaiger();
 		}
 		ifs.close();
 		Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
@@ -400,7 +400,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		log_assert(!design->module(ID($__abc9__)));
 
 		AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-		reader.parse_xaiger(box_lookup);
+		reader.parse_xaiger();
 		ifs.close();
 
 #if 0
@@ -967,45 +967,6 @@ struct Abc9Pass : public Pass {
 		if (!box_file.empty() && !is_absolute_path(box_file) && box_file[0] != '+')
 		    box_file = std::string(pwd) + "/" + box_file;
 
-		dict<int,IdString> box_lookup;
-		for (auto m : design->modules()) {
-			auto it = m->attributes.find(ID(abc9_box_id));
-			if (it == m->attributes.end())
-				continue;
-			if (m->name.begins_with("$paramod"))
-				continue;
-			auto id = it->second.as_int();
-			auto r = box_lookup.insert(std::make_pair(id, m->name));
-			if (!r.second)
-				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-						log_id(m), id, log_id(r.first->second));
-			log_assert(r.second);
-
-			RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-			for (auto p : m->ports) {
-				auto w = m->wire(p);
-				log_assert(w);
-				if (w->attributes.count(ID(abc9_carry))) {
-					if (w->port_input) {
-						if (carry_in)
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_in = w;
-					}
-					else if (w->port_output) {
-						if (carry_out)
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_out = w;
-					}
-				}
-			}
-			if (carry_in || carry_out) {
-				if (carry_in && !carry_out)
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-				if (!carry_in && carry_out)
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-			}
-		}
-
 		SigMap assign_map;
 		CellTypes ct(design);
 		for (auto module : design->selected_modules())
@@ -1056,7 +1017,7 @@ struct Abc9Pass : public Pass {
 			design->selected_active_module = module->name.str();
 			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs,
 					delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
-					box_file, lut_file, wire_delay, box_lookup, nomfs);
+					box_file, lut_file, wire_delay, nomfs);
 			design->selected_active_module.clear();
 		}
 
-- 
cgit v1.2.3


From b2046a2114add3d24c0affd9d885b7ee320dba27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:29:29 -0800
Subject: Cleanup ecp5 boxes

---
 techlibs/ecp5/abc9_5g.box  | 41 +++++++++++++++++------------------------
 techlibs/ecp5/abc9_map.v   | 19 +++++++++++--------
 techlibs/ecp5/abc9_model.v |  2 +-
 techlibs/ecp5/abc9_unmap.v |  4 ++--
 4 files changed, 31 insertions(+), 35 deletions(-)

diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
index 2bc945a54..5c7f52ab1 100644
--- a/techlibs/ecp5/abc9_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -1,43 +1,36 @@
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
 # Box 1 : CCU2C (2xCARRY + 2xLUT4)
-# Outputs: S0, S1, COUT
-#   (NB: carry chain input/output must be last
-#        input/output and bus has been moved
-#        there overriding the otherwise
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
+#        moved there overriding the otherwise
 #        alphabetical ordering)
 # name  ID   w/b   ins    outs
 CCU2C   1      1   9      3
-
-#A0   A1   B0   B1   C0    C1  D0   D1   CIN
-379  -    379  -    275   -    141  -    257
-630  379  630  379  526   275  392  141  273
-516  516  516  516  412   412  278  278  43
+#A0  B0   C0    D0   A1   B1   C1   D1   CIN
+379  379  275   141  -    -    -    -    257 # S0
+630  630  526   392  379  379  275  141  273 # S1
+516  516  412   278  516  516  412  278   43 # COUT
 
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
 $__ABC9_DPR16X4_COMB  2     0   8    4
-
-#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
+#$D0  $D1  $D2  $D3  RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379 # DO0
+0     0    0    0    141    379    275    379 # DO1
+0     0    0    0    141    379    275    379 # DO2
+0     0    0    0    141    379    275    379 # DO3
 
 # Box 3 : PFUMX (MUX2)
-# Outputs: Z
 # name  ID   w/b   ins    outs
 PFUMX   3    1     3      1
-
 #ALUT  BLUT  C0
-98     98    151
+98     98    151 # Z
 
 # Box 4 : L6MUX21 (MUX2)
-# Outputs: Z
 # name   ID   w/b   ins    outs
 L6MUX21  4    1     3      1
-
 #D0    D1    SD
-140    141   148
+140    141   148 # Z
diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v
index d8d70f9f6..113a35b91 100644
--- a/techlibs/ecp5/abc9_map.v
+++ b/techlibs/ecp5/abc9_map.v
@@ -1,24 +1,27 @@
 // ---------------------------------------
 
+// Attach a (combinatorial) black-box onto the output
+//   of this LUTRAM primitive to capture its
+//   asynchronous read behaviour
 module TRELLIS_DPR16X4 (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
+	(* techmap_autopurge *) input  [3:0] DI,
+	(* techmap_autopurge *) input  [3:0] WAD,
+	(* techmap_autopurge *) input        WRE,
+	(* techmap_autopurge *) input        WCK,
+	(* techmap_autopurge *) input  [3:0] RAD,
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter [63:0] INITVAL = 64'h0000000000000000;
-    wire [3:0] \$DO ;
+    wire [3:0] $DO;
 
     TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(\$DO )
+      .RAD(RAD), .DO($DO)
     );
 
-    \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+    $__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO));
 endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
index 1dc8b5617..81e5cd070 100644
--- a/techlibs/ecp5/abc9_model.v
+++ b/techlibs/ecp5/abc9_model.v
@@ -1,5 +1,5 @@
 // ---------------------------------------
 
 (* abc9_box_id=2 *)
-module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
 endmodule
diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v
index 9ae143c46..cbdffdaf1 100644
--- a/techlibs/ecp5/abc9_unmap.v
+++ b/techlibs/ecp5/abc9_unmap.v
@@ -1,5 +1,5 @@
 // ---------------------------------------
 
-module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-    assign Y = A;
+module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
+    assign DO = $DO;
 endmodule
-- 
cgit v1.2.3


From 2358320f5168edd691882bba0f759d82308291d6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:29:37 -0800
Subject: Cleanup ice40 boxes

---
 techlibs/ice40/abc9_hx.box | 24 ++++++++++++++----------
 techlibs/ice40/abc9_lp.box | 24 ++++++++++++++----------
 techlibs/ice40/abc9_u.box  | 25 +++++++++++++++----------
 3 files changed, 43 insertions(+), 30 deletions(-)

diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box
index 3ea70bc91..31e743669 100644
--- a/techlibs/ice40/abc9_hx.box
+++ b/techlibs/ice40/abc9_hx.box
@@ -1,13 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-#   (NB: carry chain input/output must be last
-#        input/output and have been moved there
-#        overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-400 379 449 316 316
-259 231 -   -   126
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+#                                 SB_LUT4+SB_CARRY)
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
+#        moved there overriding the otherwise
+#        alphabetical ordering)
+# name                 ID  w/b ins outs
+$__ICE40_CARRY_WRAPPER 1   1   5   2
+#A  B   I0  I3  CI
+400 379 449 316 316 # O
+259 231 -   -   126 # CO
diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box
index 473e92fe9..71986a67b 100644
--- a/techlibs/ice40/abc9_lp.box
+++ b/techlibs/ice40/abc9_lp.box
@@ -1,13 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-#   (NB: carry chain input/output must be last
-#        input/output and have been moved there
-#        overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-589 558 661 465 465
-675 609 -   -   186
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+#                                 SB_LUT4+SB_CARRY)
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
+#        moved there overriding the otherwise
+#        alphabetical ordering)
+# name                 ID  w/b ins outs
+$__ICE40_CARRY_WRAPPER 1   1   5   2
+#A  B   I0  I3  CI
+589 558 661 465 465 # O
+675 609 -   -   186 # CO
diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box
index f00e247b8..48a51463e 100644
--- a/techlibs/ice40/abc9_u.box
+++ b/techlibs/ice40/abc9_u.box
@@ -1,13 +1,18 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
 
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
-# Inputs: A B I0 I3 CI
-# Outputs: O CO
-#   (NB: carry chain input/output must be last
-#        input/output and have been moved there
-#        overriding the alphabetical ordering)
-$__ICE40_CARRY_WRAPPER 1 1 5 2
-1231 1205 1285 874 874
-675  609  -    -   278
+# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
+#                                 SB_LUT4+SB_CARRY)
+# Outputs: O, CO
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
+#        moved there overriding the otherwise
+#        alphabetical ordering)
+# name                 ID  w/b ins outs
+$__ICE40_CARRY_WRAPPER 1   1   5   2
+#A  B   I0  I3  CI
+1231 1205 1285 874 874 # O
+675  609  -    -   278 # CO
-- 
cgit v1.2.3


From 35c659be74396db7824bc98428137dc9a5ac1d16 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:29:44 -0800
Subject: Cleanup xilinx boxes

---
 techlibs/xilinx/abc9_map.v   |   3 +
 techlibs/xilinx/abc9_xc7.box | 813 ++++++++++++++++++++++---------------------
 2 files changed, 425 insertions(+), 391 deletions(-)

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index a3f9e311e..4ab8e1564 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -462,6 +462,9 @@ module FDSE_1 (output Q, input C, CE, D, S);
 `endif
 endmodule
 
+// Attach a (combinatorial) black-box onto the output
+//   of thes LUTRAM primitives to capture their
+//   asynchronous read behaviour
 module RAM32X1D (
   output DPO, SPO,
   (* techmap_autopurge *) input  D,
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 67523124a..302487041 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -5,126 +5,138 @@
 #     as their corresponding module definition
 #     (with exceptions detailed below)
 
-# Average across F7[AB]MUX
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF7 1 1 3 1
-204 208 286
+# Box 1 : MUXF7
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
+# name ID w/b ins outs
+MUXF7  1  1   3   1
+#I0 I1  S0
+204 208 286 # O
 
-# Inputs: I0 I1 S0
-# Outputs: O
-MUXF8 2 1 3 1
-104 94 273
+# Box 2 : MUXF8
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464
+# name ID w/b ins outs
+MUXF8  2  1   3   1
+#I0 I1 S0
+104 94 273 # O
 
-# Box containing MUXF7.[AB] + MUXF8
-#   Necessary to make these an atomic unit so that
-#   ABC cannot optimise just one of the MUXF7 away
-#   and expect to save on its delay
-# Inputs: I0 I1 I2 I3 S0 S1
-# Outputs: O
-$__MUXF78 3 1 6 1
-294 297 311 317 390 273
+# Box 3 : $__MUXF78
+#         (private cell used to preserve 2xMUXF7 + 1xMUXF8
+#          an atomic unit so that ABC cannot optimise just
+#          one of the MUXF7 away and expect to save on its
+#          delay, since MUXF8 is only reachable through an
+#          MUXF7)
+# name    ID w/b ins outs
+$__MUXF78 3  1   6   1
+#I0 I1  I2  I3  S0  S1
+294 297 311 317 390 273 # O
 
-# CARRY4 + CARRY4_[ABCD]X
-# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
-# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
+# Box 4 : CARRY4 + CARRY4_[ABCD]X
 #   (Exception: carry chain input/output must be the
 #        last input and output and the entire bus has been
 #        moved there overriding the otherwise
 #        alphabetical ordering)
-CARRY4 4 1 10 8
-482 -   -   -   -   223 -   -   -   222
-598 407 -   -   -   400 205 -   -   334
-584 556 537 -   -   523 558 226 -   239
-642 615 596 438 -   582 618 330 227 313
-536 379 -   -   -   340 -   -   -   271
-494 465 445 -   -   433 469 -   -   157
-592 540 520 356 -   512 548 292 -   228
-580 526 507 398 385 508 528 378 380 114
+#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
+# name ID w/b ins outs
+CARRY4 4  1   10  8
+#CYINIT DI0 DI1 DI2 DI3 S0  S1  S2  S3  CI
+482     -   -   -   -   223 -   -   -   222 # O0
+598     407 -   -   -   400 205 -   -   334 # O1
+584     556 537 -   -   523 558 226 -   239 # O2
+642     615 596 438 -   582 618 330 227 313 # O3
+536     379 -   -   -   340 -   -   -   271 # CO0
+494     465 445 -   -   433 469 -   -   157 # CO1
+592     540 520 356 -   512 548 292 -   228 # CO2
+580     526 507 398 385 508 528 378 380 114 # CO3
 
-# Box to emulate async behaviour of FDC*
-# Inputs: A S
-# Outputs: Y
-$__ABC9_ASYNC0 1000 1 2 1
-0 764
+# Box 1000 : $__ABC9_ASYNC0
+#            (private cell to emulate async behaviour of FDC*)
+# name         ID   w/b ins outs
+$__ABC9_ASYNC0 1000 1   2   1
+#A S
+0  764 # Y
 
-# Box to emulate async behaviour of FDP*
-# Inputs: A S
-# Outputs: Y
+# Box 1001 : $__ABC9_ASYNC1
+#            (private cell to emulate async behaviour of FDP*)
+# name         ID   w/b ins outs
 $__ABC9_ASYNC1 1001 1 2 1
-0 764
+#A S
+0  764 # Y
 
 # Flop boxes:
 # * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
 #                   https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
 # * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
 
-# Inputs: C CE D R $abc9_currQ
-# Outputs: Q
-FDRE 1100 1 5 1
+# Box 1100 : FDRE
+# name ID   w/b ins outs
+FDRE   1100 1   5   1
+#C CE  D   R   $abc9_currQ
 #0 109 -46 404 0
-0 109 0 404 0 # Clamp -46ps Tsu
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE D R $abc9_currQ
-# Outputs: Q
-FDRE_1 1101 1 5 1
-#0 109 0 -46 404
-0 109 0 0 404 # Clamp -46ps Tsu
+# Box 1101 : FDRE_1
+# name ID   w/b ins outs
+FDRE_1 1101 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE CLR D $abc9_currQ
-# Outputs: Q
-FDCE 1102 1 5 1
+# Box 1102 : FDCE
+# name ID   w/b ins outs
+FDCE   1102 1   5   1
+#C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
-0 109 764 0 0 # Clamp -46ps Tsu
+0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE CLR D $abc9_currQ
-# Outputs: Q
-FDCE_1 1103 1 5 1
+# Box 1103 : FDCE_1
+# name ID   w/b ins outs
+FDCE_1 1103 1   5   1
+#C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
-0 109 764 0 0 # Clamp -46ps Tsu
+0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE D PRE $abc9_currQ
-# Outputs: Q
-FDPE 1104 1 5 1
+# Box 1104 : FDPE
+# name ID   w/b ins outs
+FDPE   1104 1   5   1
+#C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
-0 109 0 764 0 # Clamp -46ps Tsu
+0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE D PRE $abc9_currQ
-# Outputs: Q
-FDPE_1 1105 1 5 1
+# Box 1105 : FDPE_1
+# name ID   w/b ins outs
+FDPE_1 1105 1   5   1
+#C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
-0 109 0 764 0 # Clamp -46ps Tsu
+0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE D S $abc9_currQ
-# Outputs: Q
-FDSE 1106 1 5 1
-#0 109 -46 446 0
-0 109 0 446 0 # Clamp -46ps Tsu
+# Box 1106 : FDSE
+# name ID   w/b ins outs
+FDSE   1106 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
-# Inputs: C CE D S $abc9_currQ
-# Outputs: Q
-FDSE_1 1107 1 5 1
-#0 109 -46 446 0
-0 109 0 446 0 # Clamp -46ps Tsu
+# Box 1107 : FDSE_1
+# name ID   w/b ins outs
+FDSE_1 1107 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
+# Box 2000 : $__ABC9_LUT6
+#            (private cell to emulate async behaviour of LUTRAMs)
 # SLICEM/A6LUT
-# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
-#   Necessary since RAMD* and SRL* have both combinatorial (i.e.
-#   same-cycle read operation) and sequential (write operation
-#   is only committed on the next clock edge).
-#   To model the combinatorial path, such cells have to be split
-#   into comb and seq parts, with this box modelling only the former.
-# Inputs: A S0 S1 S2 S3 S4 S5
-# Outputs: Y
-$__ABC9_LUT6 2000 0 7 1
-0 642 631 472 407 238 127
+# name       ID   w/b ins outs
+$__ABC9_LUT6 2000 0   7   1
+#A S0  S1  S2  S3  S4  S5
+0  642 631 472 407 238 127 # Y
 
-# SLICEM/A6LUT + F7BMUX
-# Box to emulate comb/seq behaviour of RAMD128
-# Inputs: A S0 S1 S2 S3 S4 S5 S6
-# Outputs: Y
+# Box 2001 : $__ABC9_LUT6
+#            (private cell to emulate async behaviour of LUITRAMs)
+# name       ID   w/b ins outs
 $__ABC9_LUT7 2001 0 8 1
-0 1047 1036 877 812 643 532 478
+#A S0   S1   S2  S3  S4  S5  S6
+0  1047 1036 877 812 643 532 478 # Y
 
 # Boxes used to represent the comb/seq behaviour of DSP48E1
 #   With abc9_map.v responsible for disconnecting inputs to
@@ -136,308 +148,323 @@ $__ABC9_LUT7 2001 0 8 1
 #   the mux at zero time, the combinatorial delay through
 #   these muxes thus represents the clock-to-q delay at
 #   P/PCOUT.
-$__ABC9_DSP48E1_MULT_P_MUX 2100 0 103 48
-# A AD    B    C D                                                                                               I    M P                                                                                                Pq
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
-2952 - 2813 1687 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329
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-# A    AD    B    C    D                                                                                               I    M P                                                                                                Pq
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+$__ABC9_DSP48E1 3002 0   263 154
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 - - 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 -
-- 
cgit v1.2.3


From f7793a29564881245239e81326e0c7afeb15f6e9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:42:11 -0800
Subject: Missing character

---
 techlibs/ecp5/abc9_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
index 5c7f52ab1..f153a665e 100644
--- a/techlibs/ecp5/abc9_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -17,7 +17,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # name               ID  w/b   ins   outs
 $__ABC9_DPR16X4_COMB  2     0   8    4
-#$D0  $D1  $D2  $D3  RAD0   RAD1   RAD2   RAD3
+#$DO0 $DO1 $DO2 $DO3 RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379 # DO0
 0     0    0    0    141    379    275    379 # DO1
 0     0    0    0    141    379    275    379 # DO2
-- 
cgit v1.2.3


From 44d9fb0e7cee7d8986ed037429e3c9fdd1b29ba1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:47:38 -0800
Subject: Re-arrange FD order

---
 techlibs/xilinx/abc9_map.v   | 166 +++++++++++++++++++++----------------------
 techlibs/xilinx/abc9_xc7.box |  44 ++++++------
 techlibs/xilinx/cells_sim.v  | 154 +++++++++++++++++++--------------------
 3 files changed, 182 insertions(+), 182 deletions(-)

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 4ab8e1564..6d93e508f 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -163,6 +163,89 @@ module FDRE_1 (output Q, input C, CE, D, R);
 `endif
 endmodule
 
+module FDSE (output Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+`ifdef DFF_MODE
+  wire QQ, $Q;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_R_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_S_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+
+  // Special signals
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_S_INVERTED(IS_S_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
+endmodule
+module FDSE_1 (output Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b1;
+`ifdef DFF_MODE
+  wire QQ, $Q;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+
+  // Special signals
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
+endmodule
+
 module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -379,89 +462,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
 `endif
 endmodule
 
-module FDSE (output Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b1;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
-`ifdef DFF_MODE
-  wire QQ, $Q;
-  generate if (INIT == 1'b1) begin
-    assign Q = ~QQ;
-    FDRE #(
-      .INIT(1'b0),
-      .IS_C_INVERTED(IS_C_INVERTED),
-      .IS_D_INVERTED(IS_D_INVERTED),
-      .IS_R_INVERTED(IS_S_INVERTED)
-    ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
-    );
-  end
-  else begin
-    assign Q = QQ;
-    FDSE #(
-      .INIT(1'b0),
-      .IS_C_INVERTED(IS_C_INVERTED),
-      .IS_D_INVERTED(IS_D_INVERTED),
-      .IS_S_INVERTED(IS_S_INVERTED)
-    ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
-    );
-  end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
-
-  // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_S_INVERTED(IS_S_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
-endmodule
-module FDSE_1 (output Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
-  wire QQ, $Q;
-  generate if (INIT == 1'b1) begin
-    assign Q = ~QQ;
-    FDRE_1 #(
-      .INIT(1'b0)
-    ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
-    );
-  end
-  else begin
-    assign Q = QQ;
-    FDSE_1 #(
-      .INIT(1'b0)
-    ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
-    );
-  end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
-
-  // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
-endmodule
-
 // Attach a (combinatorial) black-box onto the output
 //   of thes LUTRAM primitives to capture their
 //   asynchronous read behaviour
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 302487041..43c39544e 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -81,48 +81,48 @@ FDRE_1 1101 1   5   1
 #0 109 -46 404 0
 0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1102 : FDCE
+# Box 1102 : FDSE
 # name ID   w/b ins outs
-FDCE   1102 1   5   1
+FDSE   1102 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1103 : FDSE_1
+# name ID   w/b ins outs
+FDSE_1 1103 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1104 : FDCE
+# name ID   w/b ins outs
+FDCE   1104 1   5   1
 #C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
 0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1103 : FDCE_1
+# Box 1105 : FDCE_1
 # name ID   w/b ins outs
-FDCE_1 1103 1   5   1
+FDCE_1 1105 1   5   1
 #C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
 0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1104 : FDPE
+# Box 1106 : FDPE
 # name ID   w/b ins outs
-FDPE   1104 1   5   1
+FDPE   1106 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1105 : FDPE_1
+# Box 1107 : FDPE_1
 # name ID   w/b ins outs
-FDPE_1 1105 1   5   1
+FDPE_1 1107 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1106 : FDSE
-# name ID   w/b ins outs
-FDSE   1106 1   5   1
-#C CE  D   R   $abc9_currQ
-#0 109 -46 404 0
-0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
-
-# Box 1107 : FDSE_1
-# name ID   w/b ins outs
-FDSE_1 1107 1   5   1
-#C CE  D   R   $abc9_currQ
-#0 109 -46 404 0
-0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
-
 # Box 2000 : $__ABC9_LUT6
 #            (private cell to emulate async behaviour of LUTRAMs)
 # SLICEM/A6LUT
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 982ccad72..c22bcdc27 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -362,6 +362,43 @@ module FDRE_1 (
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
+(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
+module FDSE (
+  (* abc9_arrival=303 *)
+  output reg Q,
+  (* clkbuf_sink *)
+  (* invertible_pin = "IS_C_INVERTED" *)
+  input C,
+  input CE,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D,
+  (* invertible_pin = "IS_S_INVERTED" *)
+  input S
+);
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+  initial Q <= INIT;
+  generate case (|IS_C_INVERTED)
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
+endmodule
+
+(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
+module FDSE_1 (
+  (* abc9_arrival=303 *)
+  output reg Q,
+  (* clkbuf_sink *)
+  input C,
+  input CE, D, S
+);
+  parameter [0:0] INIT = 1'b1;
+  initial Q <= INIT;
+  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+endmodule
+
 module FDRSE (
   output reg Q,
   (* clkbuf_sink *)
@@ -397,7 +434,7 @@ module FDRSE (
       Q <= d;
 endmodule
 
-(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
 module FDCE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -423,7 +460,7 @@ module FDCE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
 module FDCE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -436,52 +473,7 @@ module FDCE_1 (
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDCPE (
-  output wire Q,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_C_INVERTED" *)
-  input C,
-  input CE,
-  (* invertible_pin = "IS_CLR_INVERTED" *)
-  input CLR,
-  input D,
-  (* invertible_pin = "IS_PRE_INVERTED" *)
-  input PRE
-);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire c = C ^ IS_C_INVERTED;
-  wire clr = CLR ^ IS_CLR_INVERTED;
-  wire pre = PRE ^ IS_PRE_INVERTED;
-  // Hacky model to avoid simulation-synthesis mismatches.
-  reg qc, qp, qs;
-  initial qc = INIT;
-  initial qp = INIT;
-  initial qs = 0;
-  always @(posedge c, posedge clr) begin
-    if (clr)
-      qc <= 0;
-    else if (CE)
-      qc <= D;
-  end
-  always @(posedge c, posedge pre) begin
-    if (pre)
-      qp <= 1;
-    else if (CE)
-      qp <= D;
-  end
-  always @* begin
-    if (clr)
-      qs <= 0;
-    else if (pre)
-      qs <= 1;
-  end
-  assign Q = qs ? qp : qc;
-endmodule
-
-(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
 module FDPE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -507,7 +499,7 @@ module FDPE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
 module FDPE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -520,41 +512,49 @@ module FDPE_1 (
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
-module FDSE (
-  (* abc9_arrival=303 *)
-  output reg Q,
+module FDCPE (
+  output wire Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   input CE,
-  (* invertible_pin = "IS_D_INVERTED" *)
+  (* invertible_pin = "IS_CLR_INVERTED" *)
+  input CLR,
   input D,
-  (* invertible_pin = "IS_S_INVERTED" *)
-  input S
+  (* invertible_pin = "IS_PRE_INVERTED" *)
+  input PRE
 );
-  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
-  initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
-endmodule
-
-(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
-module FDSE_1 (
-  (* abc9_arrival=303 *)
-  output reg Q,
-  (* clkbuf_sink *)
-  input C,
-  input CE, D, S
-);
-  parameter [0:0] INIT = 1'b1;
-  initial Q <= INIT;
-  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire c = C ^ IS_C_INVERTED;
+  wire clr = CLR ^ IS_CLR_INVERTED;
+  wire pre = PRE ^ IS_PRE_INVERTED;
+  // Hacky model to avoid simulation-synthesis mismatches.
+  reg qc, qp, qs;
+  initial qc = INIT;
+  initial qp = INIT;
+  initial qs = 0;
+  always @(posedge c, posedge clr) begin
+    if (clr)
+      qc <= 0;
+    else if (CE)
+      qc <= D;
+  end
+  always @(posedge c, posedge pre) begin
+    if (pre)
+      qp <= 1;
+    else if (CE)
+      qp <= D;
+  end
+  always @* begin
+    if (clr)
+      qs <= 0;
+    else if (pre)
+      qs <= 1;
+  end
+  assign Q = qs ? qp : qc;
 endmodule
 
 module LDCE (
-- 
cgit v1.2.3


From ac808c5e2aa0fbcfb5b56160131fcc61ba13da05 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 22:54:56 -0800
Subject: attributes.count() -> get_bool_attribute()

---
 backends/aiger/xaiger.cc | 2 +-
 passes/techmap/abc9.cc   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index be900f0e7..77659b4d8 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -284,7 +284,7 @@ struct XAigerWriter
 
                                         toposort.node(cell->name);
 
-                                        if (inst_module->attributes.count("\\abc9_flop"))
+                                        if (inst_module->get_bool_attribute("\\abc9_flop"))
                                                 flop_boxes.push_back(cell);
                                         continue;
                                 }
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3c53a5223..d6c8260b2 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 			}
 
 			RTLIL::Module* box_module = design->module(mapped_cell->type);
-			auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
+			auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop");
 			for (auto &conn : mapped_cell->connections()) {
 				RTLIL::SigSpec newsig;
 				for (auto c : conn.second.chunks()) {
@@ -988,7 +988,7 @@ struct Abc9Pass : public Pass {
 
 			for (auto cell : all_cells) {
 				auto inst_module = design->module(cell->type);
-				if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
+				if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop")
 						|| cell->get_bool_attribute("\\abc9_keep"))
 					continue;
 
-- 
cgit v1.2.3


From c40b1aae42c91f200194f7f5f2caa512787ed5a3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 08:34:43 -0800
Subject: Restore abc9 -keepff

---
 README.md                       |  3 --
 passes/techmap/abc9.cc          | 79 ++++++++++++++++++------------------
 techlibs/xilinx/abc9_map.v      | 88 ++---------------------------------------
 techlibs/xilinx/synth_xilinx.cc |  4 +-
 4 files changed, 46 insertions(+), 128 deletions(-)

diff --git a/README.md b/README.md
index c04e2b9ec..aab1c7d6b 100644
--- a/README.md
+++ b/README.md
@@ -381,9 +381,6 @@ Verilog Attributes and non-standard features
 - The module attribute ``abc9_flop`` is a boolean marking the module as a
   whitebox that describes the synchronous behaviour of a flip-flop.
 
-- The cell attribute ``abc9_keep`` is a boolean indicating that this black/
-  white box should be preserved through `abc9` mapping.
-
 - The frontend sets attributes ``always_comb``, ``always_latch`` and
   ``always_ff`` on processes derived from SystemVerilog style always blocks
   according to the type of the always. These are checked for correctness in
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index d6c8260b2..a02b8d73b 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -249,7 +249,7 @@ struct abc9_output_filter
 };
 
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
-		bool cleanup, vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
+		bool cleanup, vector<int> lut_costs, bool keepff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
 		const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
 		std::string wire_delay, bool nomfs
 )
@@ -425,19 +425,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 				module->remove(cell);
 				continue;
 			}
+			RTLIL::Module* box_module = design->module(cell->type);
 			auto jt = abc9_box.find(cell->type);
-			if (jt == abc9_box.end()) {
-				RTLIL::Module* box_module = design->module(cell->type);
+			if (jt == abc9_box.end())
 				jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
-			}
 			if (jt->second) {
-				auto kt = cell->attributes.find("\\abc9_keep");
-				bool abc9_keep = false;
-				if (kt != cell->attributes.end()) {
-					abc9_keep = kt->second.as_bool();
-					cell->attributes.erase(kt);
-				}
-				if (!abc9_keep)
+				if (!keepff || !box_module->get_bool_attribute("\\abc9_flop"))
 					boxes.emplace_back(cell);
 			}
 		}
@@ -802,6 +795,10 @@ struct Abc9Pass : public Pass {
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
 		log("\n");
+		log("    -keepff\n");
+		log("        set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
+		log("        them, for example for equivalence checking.)\n");
+		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
 		log("        are not removed. this is useful for debugging.\n");
@@ -840,7 +837,7 @@ struct Abc9Pass : public Pass {
 #endif
 		std::string script_file, clk_str, box_file, lut_file;
 		std::string delay_target, lutin_shared = "-S 1", wire_delay;
-		bool fast_mode = false, cleanup = true;
+		bool fast_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false;
 		bool nomfs = false;
 		vector<int> lut_costs;
@@ -931,6 +928,10 @@ struct Abc9Pass : public Pass {
 				fast_mode = true;
 				continue;
 			}
+			if (arg == "-keepff") {
+				keepff = true;
+				continue;
+			}
 			if (arg == "-nocleanup") {
 				cleanup = false;
 				continue;
@@ -986,36 +987,36 @@ struct Abc9Pass : public Pass {
 
 			const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
 
-			for (auto cell : all_cells) {
-				auto inst_module = design->module(cell->type);
-				if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop")
-						|| cell->get_bool_attribute("\\abc9_keep"))
-					continue;
+			if (!keepff)
+				for (auto cell : all_cells) {
+					auto inst_module = design->module(cell->type);
+					if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
+						continue;
 
-				Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
-				if (abc9_clock_wire == NULL)
-					log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				SigSpec abc9_clock = assign_map(abc9_clock_wire);
-
-				clkdomain_t key(abc9_clock);
-
-				auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-				auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-				log_assert(r2.second);
-
-				Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
-				if (abc9_init_wire == NULL)
-				    log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				log_assert(GetSize(abc9_init_wire) == 1);
-				SigSpec abc9_init = assign_map(abc9_init_wire);
-				if (!abc9_init.is_fully_const())
-				    log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-				r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
-				log_assert(r2.second);
-			}
+					Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
+					if (abc9_clock_wire == NULL)
+						log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+					SigSpec abc9_clock = assign_map(abc9_clock_wire);
+
+					clkdomain_t key(abc9_clock);
+
+					auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
+					auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
+					log_assert(r2.second);
+
+					Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
+					if (abc9_init_wire == NULL)
+						log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+					log_assert(GetSize(abc9_init_wire) == 1);
+					SigSpec abc9_init = assign_map(abc9_init_wire);
+					if (!abc9_init.is_fully_const())
+						log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+					r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+					log_assert(r2.second);
+				}
 
 			design->selected_active_module = module->name.str();
-			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs,
+			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, keepff,
 					delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
 					box_file, lut_file, wire_delay, nomfs);
 			design->selected_active_module.clear();
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 6d93e508f..1b58c34c0 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -21,7 +21,8 @@
 // The following techmapping rules are intended to be run (with -max_iter 1)
 //   before invoking the `abc9` pass in order to transform the design into
 //   a format that it understands.
-//
+
+`ifdef DFF_MODE
 // For example, (complex) flip-flops are expected to be described as an
 //   combinatorial box (containing all control logic such as clock enable
 //   or synchronous resets) followed by a basic D-Q flop.
@@ -83,7 +84,6 @@ module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -114,21 +114,9 @@ module FDRE (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-`endif
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -153,14 +141,6 @@ module FDRE_1 (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDRE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-`endif
 endmodule
 
 module FDSE (output Q, input C, CE, D, S);
@@ -168,7 +148,6 @@ module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -198,21 +177,9 @@ module FDSE (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_S_INVERTED(IS_S_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
   wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -236,14 +203,6 @@ module FDSE_1 (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
 endmodule
 
 module FDCE (output Q, input C, CE, D, CLR);
@@ -251,7 +210,6 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -295,21 +253,9 @@ module FDCE (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-`endif
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -345,14 +291,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDCE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-`endif
 endmodule
 
 module FDPE (output Q, input C, CE, D, PRE);
@@ -360,7 +298,6 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -402,21 +339,9 @@ module FDPE (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-`endif
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
   wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -452,15 +377,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
-`else
-  (* abc9_keep *)
-  FDPE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-`endif
 endmodule
+`endif
 
 // Attach a (combinatorial) black-box onto the output
 //   of thes LUTRAM primitives to capture their
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f2a9ae982..10aa7be5f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
-		log("        run 'abc9' with -dff option\n");
+		log("        enable sequential synthesis with 'abc9'\n");
 		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
@@ -559,6 +559,8 @@ struct SynthXilinxPass : public ScriptPass
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+				if (!dff_mode)
+					abc9_opts += " -keepff";
 				run("abc9" + abc9_opts);
 				run("techmap -map +/xilinx/abc9_unmap.v");
 			}
-- 
cgit v1.2.3


From 6dc63e84ef680465d500bf35da64fade626498b6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 08:34:57 -0800
Subject: Cleanup abc9, update doc for -keepff option

---
 passes/techmap/abc9.cc | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index a02b8d73b..c3c8e0dbc 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -250,7 +250,7 @@ struct abc9_output_filter
 
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
 		bool cleanup, vector<int> lut_costs, bool keepff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
+		bool show_tempdir, std::string box_file, std::string lut_file,
 		std::string wire_delay, bool nomfs
 )
 {
@@ -796,8 +796,8 @@ struct Abc9Pass : public Pass {
 		log("        2, 3, .. inputs.\n");
 		log("\n");
 		log("    -keepff\n");
-		log("        set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
-		log("        them, for example for equivalence checking.)\n");
+		log("        do not represent (* abc9_flop *) modules as boxes (and thus do not perform\n");
+		log("        any form of sequential synthesis).\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
@@ -985,10 +985,9 @@ struct Abc9Pass : public Pass {
 			typedef SigSpec clkdomain_t;
 			dict<clkdomain_t, int> clk_to_mergeability;
 
-			const std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
 
 			if (!keepff)
-				for (auto cell : all_cells) {
+				for (auto cell : module->selected_cells()) {
 					auto inst_module = design->module(cell->type);
 					if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
 						continue;
@@ -1017,7 +1016,7 @@ struct Abc9Pass : public Pass {
 
 			design->selected_active_module = module->name.str();
 			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, keepff,
-					delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
+					delay_target, lutin_shared, fast_mode, show_tempdir,
 					box_file, lut_file, wire_delay, nomfs);
 			design->selected_active_module.clear();
 		}
-- 
cgit v1.2.3


From 11577b46fcfa6c9aef4c3ed83e508ab07bc722c7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 08:38:23 -0800
Subject: Get rid of (* abc9_keep *) in write_xaiger too

---
 backends/aiger/xaiger.cc | 33 ++++++++++++++++++---------------
 1 file changed, 18 insertions(+), 15 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 77659b4d8..9c6152dff 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -250,7 +250,12 @@ struct XAigerWriter
 
 			RTLIL::Module* inst_module = module->design->module(cell->type);
 			if (inst_module) {
-				bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep");
+				bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
+				bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
+				// The lack of an abc9_mergeability attribute indicates that
+				//   we do want to keep this flop, so do not treat it as a box
+				if (abc9_flop && !cell->attributes.count("\\abc9_mergeability"))
+					abc9_box = false;
 
 				for (const auto &conn : cell->connections()) {
 					auto port_wire = inst_module->wire(conn.first);
@@ -279,15 +284,15 @@ struct XAigerWriter
 					}
 				}
 
-                                if (abc9_box) {
-                                        abc9_box_seen = true;
+				if (abc9_box) {
+					abc9_box_seen = true;
 
-                                        toposort.node(cell->name);
+					toposort.node(cell->name);
 
-                                        if (inst_module->get_bool_attribute("\\abc9_flop"))
-                                                flop_boxes.push_back(cell);
-                                        continue;
-                                }
+					if (abc9_flop)
+						flop_boxes.push_back(cell);
+					continue;
+				}
 			}
 
 			bool cell_known = inst_module || cell->known();
@@ -322,11 +327,12 @@ struct XAigerWriter
 				SigBit d;
 				if (r.second) {
 					for (const auto &conn : cell->connections()) {
-						const SigSpec &rhs = conn.second;
-						if (!rhs.is_bit())
+						if (!conn.second.is_bit())
 							continue;
-						if (!ff_bits.count(rhs))
+						d = conn.second;
+						if (!ff_bits.count(d))
 							continue;
+
 						r.first->second.first = conn.first;
 						Module *inst_module = module->design->module(cell->type);
 						Wire *wire = inst_module->wire(conn.first);
@@ -337,7 +343,6 @@ struct XAigerWriter
 								log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
 							r.first->second.second = jt->second.as_int();
 						}
-						d = rhs;
 						log_assert(d == sigmap(d));
 						break;
 					}
@@ -399,8 +404,7 @@ struct XAigerWriter
 				log_assert(cell);
 
 				RTLIL::Module* box_module = module->design->module(cell->type);
-				if (!box_module || !box_module->attributes.count("\\abc9_box_id")
-						|| cell->get_bool_attribute("\\abc9_keep"))
+				if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
 					continue;
 
 				bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
@@ -434,7 +438,6 @@ struct XAigerWriter
 					if (carry_in == IdString() && carry_out != IdString())
 						log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
 					if (carry_in != IdString()) {
-						log_assert(carry_out != IdString());
 						r.first->second.push_back(carry_in);
 						r.first->second.push_back(carry_out);
 					}
-- 
cgit v1.2.3


From 0e95756e960f809aaa4596ba44330e7bd6fd0309 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 08:39:00 -0800
Subject: Clamp -46ps for FDPE* too

---
 techlibs/xilinx/abc9_xc7.box | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 43c39544e..1dff88509 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -114,14 +114,14 @@ FDCE_1 1105 1   5   1
 FDPE   1106 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
-0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
+0 109 0   764 0 # Q (-46ps Tsu clamped to 0)
 
 # Box 1107 : FDPE_1
 # name ID   w/b ins outs
 FDPE_1 1107 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
-0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
+0 109 0   764 0 # Q (-46ps Tsu clamped to 0)
 
 # Box 2000 : $__ABC9_LUT6
 #            (private cell to emulate async behaviour of LUTRAMs)
-- 
cgit v1.2.3


From 8e507bd80785db9fa6723eada4214a5a06516cae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 12:36:54 -0800
Subject: abc9 -keepff -> -dff; refactor dff operations

---
 backends/aiger/xaiger.cc        | 136 ++++++++++++++--------------------------
 passes/techmap/abc9.cc          |  49 +++++++++------
 techlibs/xilinx/abc9_map.v      | 110 ++++++++++++++++----------------
 techlibs/xilinx/synth_xilinx.cc |   6 +-
 4 files changed, 135 insertions(+), 166 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 9c6152dff..053f9d835 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -82,7 +82,7 @@ struct XAigerWriter
 	dict<SigBit, SigBit> not_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	vector<SigBit> ci_bits, co_bits;
-	dict<SigBit, std::tuple<SigBit,int,int>> ff_bits;
+	dict<SigBit, Cell*> ff_bits;
 	dict<SigBit, float> arrival_times;
 
 	vector<pair<int, int>> aig_gates;
@@ -204,7 +204,6 @@ struct XAigerWriter
 		dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 		TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
 		bool abc9_box_seen = false;
-		std::vector<Cell*> flop_boxes;
 
 		for (auto cell : module->selected_cells()) {
 			if (cell->type == "$_NOT_")
@@ -236,14 +235,17 @@ struct XAigerWriter
 				continue;
 			}
 
-			if (cell->type == "$__ABC9_FF_")
+			if (cell->type == "$__ABC9_FF_" &&
+                                        // The presence of an abc9_mergeability attribute indicates
+                                        //   that we do want to pass this flop to ABC
+                                        cell->attributes.count("\\abc9_mergeability"))
 			{
 				SigBit D = sigmap(cell->getPort("\\D").as_bit());
 				SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
 				unused_bits.erase(D);
 				undriven_bits.erase(Q);
 				alias_map[Q] = D;
-				auto r = ff_bits.insert(std::make_pair(D, std::make_tuple(Q, 0, 2)));
+				auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
 				log_assert(r.second);
 				continue;
 			}
@@ -252,14 +254,25 @@ struct XAigerWriter
 			if (inst_module) {
 				bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
 				bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
-				// The lack of an abc9_mergeability attribute indicates that
-				//   we do want to keep this flop, so do not treat it as a box
-				if (abc9_flop && !cell->attributes.count("\\abc9_mergeability"))
+				if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
 					abc9_box = false;
 
 				for (const auto &conn : cell->connections()) {
 					auto port_wire = inst_module->wire(conn.first);
 
+					if (abc9_box) {
+						// Ignore inout for the sake of topographical ordering
+						if (port_wire->port_input && !port_wire->port_output)
+							for (auto bit : sigmap(conn.second))
+								bit_users[bit].insert(cell->name);
+						if (port_wire->port_output)
+							for (auto bit : sigmap(conn.second))
+								bit_drivers[bit].insert(cell->name);
+
+						if (!abc9_flop)
+							continue;
+					}
+
 					if (port_wire->port_output) {
 						int arrival = 0;
 						auto it = port_wire->attributes.find("\\abc9_arrival");
@@ -272,25 +285,11 @@ struct XAigerWriter
 							for (auto bit : sigmap(conn.second))
 								arrival_times[bit] = arrival;
 					}
-
-					if (abc9_box) {
-						// Ignore inout for the sake of topographical ordering
-						if (port_wire->port_input && !port_wire->port_output)
-							for (auto bit : sigmap(conn.second))
-								bit_users[bit].insert(cell->name);
-						if (port_wire->port_output)
-							for (auto bit : sigmap(conn.second))
-								bit_drivers[bit].insert(cell->name);
-					}
 				}
 
 				if (abc9_box) {
 					abc9_box_seen = true;
-
 					toposort.node(cell->name);
-
-					if (abc9_flop)
-						flop_boxes.push_back(cell);
 					continue;
 				}
 			}
@@ -321,61 +320,6 @@ struct XAigerWriter
 		}
 
 		if (abc9_box_seen) {
-			dict<IdString, std::pair<IdString,int>> flop_q;
-			for (auto cell : flop_boxes) {
-				auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
-				SigBit d;
-				if (r.second) {
-					for (const auto &conn : cell->connections()) {
-						if (!conn.second.is_bit())
-							continue;
-						d = conn.second;
-						if (!ff_bits.count(d))
-							continue;
-
-						r.first->second.first = conn.first;
-						Module *inst_module = module->design->module(cell->type);
-						Wire *wire = inst_module->wire(conn.first);
-						log_assert(wire);
-						auto jt = wire->attributes.find("\\abc9_arrival");
-						if (jt != wire->attributes.end()) {
-							if (jt->second.flags != 0)
-								log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
-							r.first->second.second = jt->second.as_int();
-						}
-						log_assert(d == sigmap(d));
-						break;
-					}
-				}
-				else
-					d = cell->getPort(r.first->second.first);
-
-				auto &rhs = ff_bits.at(d);
-
-				auto it = cell->attributes.find(ID(abc9_mergeability));
-				log_assert(it != cell->attributes.end());
-				std::get<1>(rhs) = it->second.as_int();
-				cell->attributes.erase(it);
-
-				it = cell->attributes.find(ID(abc9_init));
-				log_assert(it != cell->attributes.end());
-				log_assert(GetSize(it->second) == 1);
-				if (it->second[0] == State::S1)
-					std::get<2>(rhs) = 1;
-				else if (it->second[0] == State::S0)
-					std::get<2>(rhs) = 0;
-				else {
-					log_assert(it->second[0] == State::Sx);
-					std::get<2>(rhs) = 0;
-				}
-				cell->attributes.erase(it);
-
-				const SigBit &q = std::get<0>(rhs);
-				auto arrival = r.first->second.second;
-				if (arrival)
-					arrival_times[q] = arrival;
-			}
-
 			for (auto &it : bit_users)
 				if (bit_drivers.count(it.first))
 					for (auto driver_cell : bit_drivers.at(it.first))
@@ -501,11 +445,11 @@ struct XAigerWriter
 					}
 				}
 
-				// Connect <cell>.$abc9_currQ (inserted by abc9_map.v) as an input to the flop box
+				// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
 				if (box_module->get_bool_attribute("\\abc9_flop")) {
-					SigSpec rhs = module->wire(stringf("%s.$abc9_currQ", cell->name.c_str()));
+					SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
 					if (rhs.empty())
-						log_error("'%s.$abc9_currQ' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
+						log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
 
 					for (auto b : rhs) {
 						SigBit I = sigmap(b);
@@ -553,7 +497,8 @@ struct XAigerWriter
 		}
 
 		for (const auto &i : ff_bits) {
-			const SigBit &q = std::get<0>(i.second);
+			const Cell *cell = i.second;
+			const SigBit &q = sigmap(cell->getPort("\\Q"));
 			aig_m++, aig_i++;
 			log_assert(!aig_map.count(q));
 			aig_map[q] = 2*aig_m;
@@ -742,7 +687,7 @@ struct XAigerWriter
 				}
 
 				// For flops only, create an extra 1-bit input that drives a new wire
-				//   called "<cell>.$abc9_currQ" that is used below
+				//   called "<cell>.abc9_ff.Q" that is used below
 				if (box_module->get_bool_attribute("\\abc9_flop")) {
 					log_assert(holes_cell);
 
@@ -754,7 +699,8 @@ struct XAigerWriter
 						holes_wire->port_id = port_id++;
 						holes_module->ports.push_back(holes_wire->name);
 					}
-					Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
+					Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
+					log_assert(w);
 					holes_module->connect(w, holes_wire);
 				}
 
@@ -774,13 +720,25 @@ struct XAigerWriter
 			write_s_buffer(ff_bits.size());
 
 			for (const auto &i : ff_bits) {
-				const SigBit &q = std::get<0>(i.second);
-				int mergeability = std::get<1>(i.second);
+				const SigBit &d = i.first;
+				const Cell *cell = i.second;
+
+				int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
 				log_assert(mergeability > 0);
 				write_r_buffer(mergeability);
-				int init = std::get<2>(i.second);
-				write_s_buffer(init);
-				write_i_buffer(arrival_times.at(q, 0));
+
+				Const init = cell->attributes.at(ID(abc9_init));
+				log_assert(GetSize(init) == 1);
+				if (init == State::S1)
+					write_s_buffer(1);
+				else if (init == State::S0)
+					write_s_buffer(0);
+				else {
+					log_assert(init == State::Sx);
+					write_s_buffer(0);
+				}
+
+				write_i_buffer(arrival_times.at(d, 0));
 				//write_o_buffer(0);
 			}
 
@@ -833,9 +791,9 @@ struct XAigerWriter
 						log_assert(pos != std::string::npos);
 						IdString driver = Q.wire->name.substr(0, pos);
 						// And drive the signal that was previously driven by "DFF.Q" (typically
-						//   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
+						//   used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
 						//   wire (which itself is driven an input port) we inserted above
-						Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
+						Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
 						log_assert(currQ);
 						holes_module->connect(Q, currQ);
 						continue;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index c3c8e0dbc..6aa0b6f95 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -249,7 +249,7 @@ struct abc9_output_filter
 };
 
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
-		bool cleanup, vector<int> lut_costs, bool keepff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
+		bool cleanup, vector<int> lut_costs, bool dff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
 		bool show_tempdir, std::string box_file, std::string lut_file,
 		std::string wire_delay, bool nomfs
 )
@@ -347,7 +347,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
 		log_assert(!design->module(ID($__abc9__)));
 		{
-			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
+			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, /*buffer.c_str()*/ "" /* map_filename */, true /* wideports */);
 			reader.parse_xaiger();
 		}
 		ifs.close();
@@ -430,7 +430,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 			if (jt == abc9_box.end())
 				jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
 			if (jt->second) {
-				if (!keepff || !box_module->get_bool_attribute("\\abc9_flop"))
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
+					if (dff)
+						boxes.emplace_back(cell);
+					else
+						box_module->set_bool_attribute("\\abc9_keep", false);
+				}
+				else
 					boxes.emplace_back(cell);
 			}
 		}
@@ -795,9 +801,9 @@ struct Abc9Pass : public Pass {
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
 		log("\n");
-		log("    -keepff\n");
-		log("        do not represent (* abc9_flop *) modules as boxes (and thus do not perform\n");
-		log("        any form of sequential synthesis).\n");
+		log("    -dff\n");
+		log("        also pass $_ABC9_FF_ cells through ABC. modules with many clock domains\n");
+		log("        are marked as such and automatically partitioned by ABC.\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
@@ -837,7 +843,7 @@ struct Abc9Pass : public Pass {
 #endif
 		std::string script_file, clk_str, box_file, lut_file;
 		std::string delay_target, lutin_shared = "-S 1", wire_delay;
-		bool fast_mode = false, keepff = false, cleanup = true;
+		bool fast_mode = false, dff = false, cleanup = true;
 		bool show_tempdir = false;
 		bool nomfs = false;
 		vector<int> lut_costs;
@@ -928,8 +934,8 @@ struct Abc9Pass : public Pass {
 				fast_mode = true;
 				continue;
 			}
-			if (arg == "-keepff") {
-				keepff = true;
+			if (arg == "-dff") {
+				dff = true;
 				continue;
 			}
 			if (arg == "-nocleanup") {
@@ -985,16 +991,14 @@ struct Abc9Pass : public Pass {
 			typedef SigSpec clkdomain_t;
 			dict<clkdomain_t, int> clk_to_mergeability;
 
-
-			if (!keepff)
+			if (dff)
 				for (auto cell : module->selected_cells()) {
-					auto inst_module = design->module(cell->type);
-					if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
+					if (cell->type != "$__ABC9_FF_")
 						continue;
 
-					Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
+					Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
 					if (abc9_clock_wire == NULL)
-						log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+						log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 					SigSpec abc9_clock = assign_map(abc9_clock_wire);
 
 					clkdomain_t key(abc9_clock);
@@ -1003,19 +1007,26 @@ struct Abc9Pass : public Pass {
 					auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
 					log_assert(r2.second);
 
-					Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
+					Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
 					if (abc9_init_wire == NULL)
-						log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+						log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 					log_assert(GetSize(abc9_init_wire) == 1);
 					SigSpec abc9_init = assign_map(abc9_init_wire);
 					if (!abc9_init.is_fully_const())
-						log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+						log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
 					r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
 					log_assert(r2.second);
 				}
+			else
+				for (auto cell : module->selected_cells()) {
+					auto inst_module = design->module(cell->type);
+					if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
+						continue;
+					cell->set_bool_attribute("\\abc9_keep");
+				}
 
 			design->selected_active_module = module->name.str();
-			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, keepff,
+			abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, dff,
 					delay_target, lutin_shared, fast_mode, show_tempdir,
 					box_file, lut_file, wire_delay, nomfs);
 			design->selected_active_module.clear();
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 1b58c34c0..1d37952f5 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -51,29 +51,29 @@
 //                ||                  ||
 //                ||      /\/\/\/\    ||
 //           D  -->>-----<        >   ||
-//           R  -->>-----<  Comb. >   ||        +----------+
-//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q
-// $abc9_currQ +-->>-----<        >   ||        +----------+  |
-//             |  ||      \/\/\/\/    ||                      |
-//             |  ||                  ||                      |
-//             |  ++==================++                      |
-//             |                                              |
-//             +----------------------------------------------+
+//           R  -->>-----<  Comb. >   ||        +-----------+
+//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q
+//   abc9_ff.Q +-->>-----<        >   ||        +-----------+  |
+//             |  ||      \/\/\/\/    ||                       |
+//             |  ||                  ||                       |
+//             |  ++==================++                       |
+//             |                                               |
+//             +-----------------------------------------------+
 //
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
 // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
 //     capture asynchronous behaviour
-// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
+// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock
 //     domain and polarity (used when partitioning the module so that `abc9' only
 //     performs sequential synthesis (with reachability analysis) correctly on
 //     one domain at a time) and also used to infer the optional delay target
 //     from the (* abc9_clock_period = %d *) attribute attached to any wire
 //     within
-// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial
 //     state
-// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 //
 // In order to perform sequential synthesis, `abc9' also requires that
@@ -108,12 +108,12 @@ module FDRE (output Q, input C, CE, D, R);
     );
   end
   endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -135,12 +135,12 @@ module FDRE_1 (output Q, input C, CE, D, R);
     );
   end
   endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 
 module FDSE (output Q, input C, CE, D, S);
@@ -171,12 +171,12 @@ module FDSE (output Q, input C, CE, D, S);
       .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
@@ -197,12 +197,12 @@ module FDSE_1 (output Q, input C, CE, D, S);
       .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
 endmodule
 
 module FDCE (output Q, input C, CE, D, CLR);
@@ -210,7 +210,7 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE #(
@@ -227,7 +227,7 @@ module FDCE (output Q, input C, CE, D, CLR);
                                             //     $__ABC9_ASYNC1 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -245,18 +245,18 @@ module FDCE (output Q, input C, CE, D, CLR);
                                            //     $__ABC9_ASYNC0 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE_1 #(
@@ -269,7 +269,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -283,14 +283,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 
 module FDPE (output Q, input C, CE, D, PRE);
@@ -298,7 +298,7 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE #(
@@ -314,7 +314,7 @@ module FDPE (output Q, input C, CE, D, PRE);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -331,18 +331,18 @@ module FDPE (output Q, input C, CE, D, PRE);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
-  wire QQ, $Q, $abc9_currQ;
+  wire QQ, $Q, $QQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE_1 #(
@@ -355,7 +355,7 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -369,14 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ));
   end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
+  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] abc9_ff.init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
 endmodule
 `endif
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 10aa7be5f..af9f21756 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
-		log("        enable sequential synthesis with 'abc9'\n");
+		log("        run 'abc9' with -dff option\n");
 		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
@@ -559,8 +559,8 @@ struct SynthXilinxPass : public ScriptPass
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
-				if (!dff_mode)
-					abc9_opts += " -keepff";
+				if (dff_mode)
+					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);
 				run("techmap -map +/xilinx/abc9_unmap.v");
 			}
-- 
cgit v1.2.3


From ec1756c0941fac02614c25307b17bb41fe36f468 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 12:39:52 -0800
Subject: Update comments

---
 techlibs/xilinx/abc9_map.v | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 1d37952f5..af58e217c 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -65,19 +65,14 @@
 //     the connectivity of its basic D-Q flop
 // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
 //     capture asynchronous behaviour
-// (c) a special _TECHMAP_REPLACE_.abc9_ff.clock wire to capture its clock
-//     domain and polarity (used when partitioning the module so that `abc9' only
-//     performs sequential synthesis (with reachability analysis) correctly on
-//     one domain at a time) and also used to infer the optional delay target
-//     from the (* abc9_clock_period = %d *) attribute attached to any wire
-//     within
-// (d) a special _TECHMAP_REPLACE_.abc9_ff.init wire to encode the flop's initial
-//     state
+// (c) a special abc9_ff.clock wire to capture its clock domain and polarity
+//     (indicated to `abc9' so that it only performs sequential synthesis
+//     (with reachability analysis) correctly on one domain at a time)
+// (d) a special abc9_ff.init wire to encode the flop's initial state
+//     NOTE: in order to perform sequential synthesis, `abc9' also requires
+//     that the initial value of all flops be zero
 // (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
-//
-// In order to perform sequential synthesis, `abc9' also requires that
-// the initial value of all flops be zero.
 
 module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-- 
cgit v1.2.3


From ca42af56a49a7ab3a55adab22f139d34ddb147b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 12:41:57 -0800
Subject: Update doc

---
 passes/techmap/abc9.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6aa0b6f95..d39aa7638 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -802,8 +802,8 @@ struct Abc9Pass : public Pass {
 		log("        2, 3, .. inputs.\n");
 		log("\n");
 		log("    -dff\n");
-		log("        also pass $_ABC9_FF_ cells through ABC. modules with many clock domains\n");
-		log("        are marked as such and automatically partitioned by ABC.\n");
+		log("        also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
+		log("        domains are marked as such and automatically partitioned by ABC.\n");
 		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
@@ -825,8 +825,8 @@ struct Abc9Pass : public Pass {
 		log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
 		log("ABC on logic snippets extracted from your design. You will not get any useful\n");
 		log("output when passing an ABC script that writes a file. Instead write your full\n");
-		log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
-		log("if you want to use ABC to convert your design into another format.\n");
+		log("design as an XAIGER file with `write_xaiger' and then load that into ABC\n");
+		log("externally if you want to use ABC to convert your design into another format.\n");
 		log("\n");
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
 		log("\n");
-- 
cgit v1.2.3


From 345e98f87105316da9797e01bdbdd3932269cfdf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 12:42:28 -0800
Subject: Add 'abc9 -dff' to CHANGELOG

---
 CHANGELOG | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG b/CHANGELOG
index fc0cdc92e..481ba266e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -57,6 +57,7 @@ Yosys 0.9 .. Yosys 0.9-dev
       always_latch and always_ff)
     - Added "xilinx_dffopt" pass
     - Added "scratchpad" pass
+    - Added "abc9 -dff"
     - Added "synth_xilinx -dff"
 
 Yosys 0.8 .. Yosys 0.9
-- 
cgit v1.2.3


From a051801b72c7d526a1c04cf2635ae8d7fe43a135 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 12:53:26 -0800
Subject: synth_xilinx -dff to work with abc too

---
 techlibs/xilinx/synth_xilinx.cc | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e2a625f9b..51d2cbbd2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -108,10 +108,11 @@ struct SynthXilinxPass : public ScriptPass
 		log("        flatten design before synthesis\n");
 		log("\n");
 		log("    -dff\n");
-		log("        run 'abc9' with -dff option\n");
+		log("        run 'abc'/'abc9' with -dff option\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with '-dff -D 1' options\n");
+		log("        run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
+		log("        implies -dff.\n");
 		log("\n");
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
@@ -195,6 +196,7 @@ struct SynthXilinxPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-retime") {
+				dff_mode = true;
 				retime = true;
 				continue;
 			}
@@ -542,7 +544,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (flatten_before_abc)
 				run("flatten");
 			if (help_mode)
-				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
+				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
@@ -565,10 +567,16 @@ struct SynthXilinxPass : public ScriptPass
 				run("techmap -map +/xilinx/abc9_unmap.v");
 			}
 			else {
+				std::string abc_opts;
 				if (nowidelut)
-					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
+					abc_opts += " -luts 2:2,3,6:5";
 				else
-					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
+					abc_opts += " -luts 2:2,3,6:5,10,20";
+				if (dff_mode)
+					abc_opts += " -dff";
+				if (retime)
+					abc_opts += " -D 1";
+				run("abc" + abc_opts);
 			}
 			run("clean");
 
@@ -581,7 +589,7 @@ struct SynthXilinxPass : public ScriptPass
 				techmap_args += stringf("[-map %s]", ff_map_file.c_str());
 			else if (!abc9)
 				techmap_args += stringf(" -map %s", ff_map_file.c_str());
-			run("techmap " + techmap_args, "(option without '-abc9')");
+			run("techmap " + techmap_args, "(only if '-abc9')");
 			run("xilinx_dffopt");
 		}
 
-- 
cgit v1.2.3


From 6e866030c286d70f6ccff805e58b1fdd9a1a322b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 14:38:59 -0800
Subject: Combine tests to check multiple clock domains

---
 tests/arch/xilinx/abc9_dff.ys | 43 ++++++++++---------------------------------
 1 file changed, 10 insertions(+), 33 deletions(-)

diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index 6611b4f18..b457cefce 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -1,55 +1,32 @@
 read_verilog <<EOT
-module top(input C, D, output [3:0] Q);
+module top(input C, D, output [7:0] Q);
 FDRE   fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
 FDSE   fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
 FDCE   fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
 FDPE   fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
+FDRE_1 fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
+FDSE_1 fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
+FDCE_1 fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
+FDPE_1 fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
 endmodule
 EOT
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-none t:FD*
 
-
 design -reset
 read_verilog <<EOT
-module top(input C, D, output [3:0] Q);
+module top(input C, D, output [7:0] Q);
 FDRE   fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
 FDSE   fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
 FDCE   fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
 FDPE   fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+FDRE_1 fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
+FDSE_1 fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
+FDCE_1 fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
+FDPE_1 fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-none t:FD*
-
-
-design -reset
-read_verilog <<EOT
-module top(input C, D, output [3:0] Q);
-FDRE_1 fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
-FDSE_1 fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
-FDCE_1 fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
-FDPE_1 fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
-endmodule
-EOT
-
-equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
-design -load postopt
-select -assert-none t:FD*
-
-
-design -reset
-read_verilog <<EOT
-module top(input C, D, output [3:0] Q);
-FDRE_1 fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
-FDSE_1 fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
-FDCE_1 fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
-FDPE_1 fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
-endmodule
-EOT
-
-equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
-design -load postopt
-select -assert-none t:FD*
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