From 7977574995baa2cdba1401233179f9f84fe96a3a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Jan 2020 15:25:49 -0800
Subject: New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC

---
 techlibs/common/Makefile.inc |   1 +
 techlibs/common/shiftx2mux.v |  38 +++++++++++++++
 tests/techmap/shiftx2mux.ys  | 110 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 techlibs/common/shiftx2mux.v
 create mode 100644 tests/techmap/shiftx2mux.ys

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index a42f63128..5d797ec1d 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -30,3 +30,4 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
 $(eval $(call add_share_file,share,techlibs/common/dummy.box))
+$(eval $(call add_share_file,share,techlibs/common/shiftx2mux.v))
diff --git a/techlibs/common/shiftx2mux.v b/techlibs/common/shiftx2mux.v
new file mode 100644
index 000000000..5366d6749
--- /dev/null
+++ b/techlibs/common/shiftx2mux.v
@@ -0,0 +1,38 @@
+(* techmap_celltype = /*"$shift*/ "$shiftx" *)
+module _80_shift_shiftx (A, B, Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] Y;
+
+    parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+    parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
+    generate
+        genvar i;
+        localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
+
+        if (B_WIDTH <= CLOG2_Y_WIDTH+1)
+            wire _TECHMAP_FAIL_ = 1;
+        // In order to perform this optimisation, this $shiftx must
+        //   only shift in units of Y_WIDTH, which we check by ensuring
+        //   that the appropriate LSBs of B are zero
+        else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}})
+            wire _TECHMAP_FAIL_ = 1;
+        else begin
+            // Halve the size of $shiftx by $mux-ing A according to 
+            //   the LSB of B, after discarding the zeroed bits
+            wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA;
+            for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2)
+                assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH];
+            $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y));
+        end
+    endgenerate
+endmodule
+
+
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
new file mode 100644
index 000000000..acdd54e9e
--- /dev/null
+++ b/tests/techmap/shiftx2mux.ys
@@ -0,0 +1,110 @@
+read_verilog <<EOT
+module sc1 (i1 ,
+            i2 ,
+            i3 ,
+            i4 ,
+            i5 ,
+            i6 ,
+            i7 ,
+            i8 ,
+            i9 ,
+            i10,
+            i11,
+            i12,
+            i13,
+            i14,
+            i15,
+            binary_out,
+            encoder_in,
+            enable
+);
+
+input [3:0]   i1 ;
+input [3:0]   i2 ;
+input [3:0]   i3 ;
+input [3:0]   i4 ;
+input [3:0]   i5 ;
+input [3:0]   i6 ;
+input [3:0]   i7 ;
+input [3:0]   i8 ;
+input [3:0]   i9 ;
+input [3:0]   i10 ;
+input [3:0]   i11 ;
+input [3:0]   i12 ;
+input [3:0]   i13 ;
+input [3:0]   i14 ;
+input [3:0]   i15 ;
+
+output reg [3:0] binary_out  ;
+
+input [3:0] encoder_in ;
+input  enable ;
+
+
+
+always @ (*)
+begin
+	binary_out = 0;
+	if (enable) begin
+		case (encoder_in)
+			4'h1 : binary_out = i1;
+			4'h2 : binary_out = i2;
+			4'h3 : binary_out = i3;
+			4'h4 : binary_out = i4;
+			4'h5 : binary_out = i5;
+			4'h6 : binary_out = i6;
+			4'h7 : binary_out = i7;
+			4'h8 : binary_out = i8;
+			4'h9 : binary_out = i9;
+			4'ha : binary_out = i10;
+			4'hb : binary_out = i11;/*
+			4'hc : binary_out = i12;
+			4'hd : binary_out = i13;
+			4'he : binary_out = i14;
+			4'hf : binary_out = i15;*/
+	       endcase
+       end
+end
+endmodule
+EOT
+
+proc
+pmux2shiftx
+design -save gold
+
+
+design -load gold
+techmap
+abc -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap -map +/shiftx2mux.v -map +/techmap.v
+abc -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+design -load gold
+techmap
+abc9 -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap -map +/shiftx2mux.v -map +/techmap.v
+abc9 -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
-- 
cgit v1.2.3


From 8d1b736c4f3d30743f6b3a9cbab35bdb80b49153 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 14:08:24 -0800
Subject: Move from +/shiftx2mux.v into +/techmap.v; cleanup

---
 techlibs/common/Makefile.inc |   1 -
 techlibs/common/shiftx2mux.v |  38 ----------------
 techlibs/common/techmap.v    | 103 +++++++++++++++++++++++++++++--------------
 tests/techmap/shiftx2mux.ys  |   8 ++--
 4 files changed, 73 insertions(+), 77 deletions(-)
 delete mode 100644 techlibs/common/shiftx2mux.v

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 5d797ec1d..a42f63128 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -30,4 +30,3 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
 $(eval $(call add_share_file,share,techlibs/common/dummy.box))
-$(eval $(call add_share_file,share,techlibs/common/shiftx2mux.v))
diff --git a/techlibs/common/shiftx2mux.v b/techlibs/common/shiftx2mux.v
deleted file mode 100644
index 5366d6749..000000000
--- a/techlibs/common/shiftx2mux.v
+++ /dev/null
@@ -1,38 +0,0 @@
-(* techmap_celltype = /*"$shift*/ "$shiftx" *)
-module _80_shift_shiftx (A, B, Y);
-	parameter A_SIGNED = 0;
-	parameter B_SIGNED = 0;
-	parameter A_WIDTH = 1;
-	parameter B_WIDTH = 1;
-	parameter Y_WIDTH = 1;
-
-	input [A_WIDTH-1:0] A;
-	input [B_WIDTH-1:0] B;
-	output [Y_WIDTH-1:0] Y;
-
-    parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
-    parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
-
-    generate
-        genvar i;
-        localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
-
-        if (B_WIDTH <= CLOG2_Y_WIDTH+1)
-            wire _TECHMAP_FAIL_ = 1;
-        // In order to perform this optimisation, this $shiftx must
-        //   only shift in units of Y_WIDTH, which we check by ensuring
-        //   that the appropriate LSBs of B are zero
-        else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}})
-            wire _TECHMAP_FAIL_ = 1;
-        else begin
-            // Halve the size of $shiftx by $mux-ing A according to 
-            //   the LSB of B, after discarding the zeroed bits
-            wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA;
-            for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2)
-                assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH];
-            $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y));
-        end
-    endgenerate
-endmodule
-
-
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index d7ec3947e..83bd4333c 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -129,47 +129,82 @@ module _90_shift_shiftx (A, B, Y);
 	input [B_WIDTH-1:0] B;
 	output [Y_WIDTH-1:0] Y;
 
-	localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
-	localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
-
 	parameter _TECHMAP_CELLTYPE_ = "";
+	parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+	parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
 	localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
 
-	wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
-	wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
+	generate
+`ifndef NO_LSB_FIRST_SHIFT_SHIFTX
+		// If $shift/$shiftx only shifts in units of Y_WIDTH
+		//   (a common pattern created by pmux2shiftx)
+		//   which is checked by ensuring that all that
+		//   the appropriate LSBs of B are constant zero,
+		//   then we can decompose LSB first instead of
+		//   MSB first
+		localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
+		if (B_WIDTH > CLOG2_Y_WIDTH+1 &&
+			_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} &&
+			_TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin
+			// Halve the size of $shift/$shiftx by $mux-ing A according to
+			//   the LSB of B, after discarding the zeroed bits
+			localparam len = 2**(B_WIDTH-1);
+			wire [len-1:0] T, F;
+			genvar i;
+			for (i = 0; i < A_WIDTH; i=i+Y_WIDTH*2) begin
+				assign F[i/2 +: Y_WIDTH] = A[i +: Y_WIDTH];
+				assign T[i/2 +: Y_WIDTH] = (i + Y_WIDTH < A_WIDTH) ? A[i+Y_WIDTH +: Y_WIDTH] : {Y_WIDTH{extbit}};
+			end
+			wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
+			wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
+			if (_TECHMAP_CELLTYPE_ == "$shift")
+				$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
+			else
+				$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
+		end
+		else
+`endif
+		begin
+			localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
+			localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
 
-	integer i;
-	reg [WIDTH-1:0] buffer;
-	reg overflow;
+			wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
+			wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
 
-	always @* begin
-		overflow = 0;
-		buffer = {WIDTH{extbit}};
-		buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
-
-		if (B_WIDTH > BB_WIDTH) begin
-			if (B_SIGNED) begin
-				for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
-					if (B[i] != B[BB_WIDTH-1])
-						overflow = 1;
-			end else
-				overflow = |B[B_WIDTH-1:BB_WIDTH];
-			if (overflow)
-				buffer = {WIDTH{extbit}};
-		end
+			integer i;
+			reg [WIDTH-1:0] buffer;
+			reg overflow;
 
-		for (i = BB_WIDTH-1; i >= 0; i = i-1)
-			if (B[i]) begin
-				if (B_SIGNED && i == BB_WIDTH-1)
-					buffer = {buffer, {2**i{extbit}}};
-				else if (2**i < WIDTH)
-					buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
-				else
-					buffer = {WIDTH{extbit}};
+			always @* begin
+				overflow = 0;
+				buffer = {WIDTH{extbit}};
+				buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A;
+
+				if (B_WIDTH > BB_WIDTH) begin
+					if (B_SIGNED) begin
+						for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
+							if (B[i] != B[BB_WIDTH-1])
+								overflow = 1;
+					end else
+						overflow = |B[B_WIDTH-1:BB_WIDTH];
+					if (overflow)
+						buffer = {WIDTH{extbit}};
+				end
+
+				for (i = BB_WIDTH-1; i >= 0; i = i-1)
+					if (B[i]) begin
+						if (B_SIGNED && i == BB_WIDTH-1)
+							buffer = {buffer, {2**i{extbit}}};
+						else if (2**i < WIDTH)
+							buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
+						else
+							buffer = {WIDTH{extbit}};
+					end
 			end
-	end
-
-	assign Y = buffer;
+			assign Y = buffer;
+		end
+	endgenerate
 endmodule
 
 
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
index acdd54e9e..c13b5f600 100644
--- a/tests/techmap/shiftx2mux.ys
+++ b/tests/techmap/shiftx2mux.ys
@@ -74,13 +74,13 @@ design -save gold
 
 
 design -load gold
-techmap
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
 abc -lut 6
 select -assert-min 17 t:$lut
 
 
 design -load gold
-techmap -map +/shiftx2mux.v -map +/techmap.v
+techmap
 abc -lut 6
 select -assert-count 16 t:$lut
 
@@ -92,13 +92,13 @@ sat -verify -prove-asserts -show-ports miter
 
 
 design -load gold
-techmap
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
 abc9 -lut 6
 select -assert-min 17 t:$lut
 
 
 design -load gold
-techmap -map +/shiftx2mux.v -map +/techmap.v
+techmap
 abc9 -lut 6
 select -assert-count 16 t:$lut
 
-- 
cgit v1.2.3


From 152dfd3dd4ac6ea45fba3a6ed5cc7d6f5466f998 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 15:02:37 -0800
Subject: Fix tests -- when Y_WIDTH is non-pow-2

---
 techlibs/common/techmap.v | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 83bd4333c..95cfa66b2 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -150,11 +150,12 @@ module _90_shift_shiftx (A, B, Y);
 			// Halve the size of $shift/$shiftx by $mux-ing A according to
 			//   the LSB of B, after discarding the zeroed bits
 			localparam len = 2**(B_WIDTH-1);
+			localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
 			wire [len-1:0] T, F;
 			genvar i;
-			for (i = 0; i < A_WIDTH; i=i+Y_WIDTH*2) begin
-				assign F[i/2 +: Y_WIDTH] = A[i +: Y_WIDTH];
-				assign T[i/2 +: Y_WIDTH] = (i + Y_WIDTH < A_WIDTH) ? A[i+Y_WIDTH +: Y_WIDTH] : {Y_WIDTH{extbit}};
+			for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
+				assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
+				assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
 			end
 			wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
 			wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
-- 
cgit v1.2.3


From 72e4540ca9749a0b7621e91e32e5aabf24b29b74 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 16:49:34 -0800
Subject: Explicitly create separate $mux cells

---
 techlibs/common/techmap.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 95cfa66b2..75a51e55e 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -151,13 +151,13 @@ module _90_shift_shiftx (A, B, Y);
 			//   the LSB of B, after discarding the zeroed bits
 			localparam len = 2**(B_WIDTH-1);
 			localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
-			wire [len-1:0] T, F;
+			wire [len-1:0] T, F, AA;
 			genvar i;
 			for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
 				assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
 				assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
+				assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
 			end
-			wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
 			wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
 			if (_TECHMAP_CELLTYPE_ == "$shift")
 				$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
-- 
cgit v1.2.3


From 5aaa19f1ab33394accbe633cd96a3fbe281dd09a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 16:50:04 -0800
Subject: Update tests with reduced area

---
 tests/arch/ecp5/mux.ys   | 6 +++---
 tests/arch/efinix/mux.ys | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 22866832d..92463aa32 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:L6MUX21
-select -assert-count 34 t:LUT4
-select -assert-count 17 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys
index b46f641e1..a4268aea3 100644
--- a/tests/arch/efinix/mux.ys
+++ b/tests/arch/efinix/mux.ys
@@ -16,7 +16,7 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 2 t:EFX_LUT4
+#select -assert-count 2 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
 
@@ -26,7 +26,7 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 5 t:EFX_LUT4
+#select -assert-count 5 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
 
@@ -36,6 +36,6 @@ proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:EFX_LUT4
+select -assert-count 11 t:EFX_LUT4
 
 select -assert-none t:EFX_LUT4 %% t:* %D
-- 
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