From 617693e69128982ce1be91b76c541d6ae1950ad8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 8 Nov 2016 19:07:22 +0100
Subject: Progress in examples/gowin/
---
examples/gowin/.gitignore | 2 ++
examples/gowin/demo.cst | 58 ++++++++++++++++++++++++++++++++--------------
examples/gowin/demo.v | 9 +++----
examples/gowin/run.sh | 7 ++++++
examples/gowin/testbench.v | 40 ++++++++++++++++++++++++++++++++
5 files changed, 95 insertions(+), 21 deletions(-)
create mode 100644 examples/gowin/testbench.v
diff --git a/examples/gowin/.gitignore b/examples/gowin/.gitignore
index 823caa1d7..71030bdb8 100644
--- a/examples/gowin/.gitignore
+++ b/examples/gowin/.gitignore
@@ -4,3 +4,5 @@ demo.rpt
demo_syn.v
demo_out.v
demo_tr.html
+testbench
+testbench.vcd
diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst
index 0b14b5bd6..22d7eb668 100644
--- a/examples/gowin/demo.cst
+++ b/examples/gowin/demo.cst
@@ -1,17 +1,41 @@
-IO_LOC "clk" D11;
-IO_LOC "led1" D22;
-IO_LOC "led2" E22;
-IO_LOC "led3" G22;
-IO_LOC "led4" J22;
-IO_LOC "led5" L22;
-IO_LOC "led6" L19;
-IO_LOC "led7" L20;
-IO_LOC "led8" M21;
-IO_LOC "led9" N19;
-IO_LOC "led10" R19;
-IO_LOC "led11" T18;
-IO_LOC "led12" AA22;
-IO_LOC "led13" U18;
-IO_LOC "led14" V20;
-IO_LOC "led15" AA21;
-IO_LOC "led16" AB21;
+// 50 MHz Clock
+IO_LOC "clk" D11;
+
+// LEDs
+IO_LOC "leds[0]" D22;
+IO_LOC "leds[1]" E22;
+IO_LOC "leds[2]" G22;
+IO_LOC "leds[3]" J22;
+IO_LOC "leds[4]" L22;
+IO_LOC "leds[5]" L19;
+IO_LOC "leds[6]" L20;
+IO_LOC "leds[7]" M21;
+IO_LOC "leds[8]" N19;
+IO_LOC "leds[9]" R19;
+IO_LOC "leds[10]" T18;
+IO_LOC "leds[11]" AA22;
+IO_LOC "leds[12]" U18;
+IO_LOC "leds[13]" V20;
+IO_LOC "leds[14]" AA21;
+IO_LOC "leds[15]" AB21;
+
+
+// 7-Segment Display
+IO_LOC "seg7dig[0]" E20;
+IO_LOC "seg7dig[1]" G18;
+IO_LOC "seg7dig[2]" G20;
+IO_LOC "seg7dig[3]" F21;
+IO_LOC "seg7dig[4]" J20;
+IO_LOC "seg7dig[5]" H21;
+IO_LOC "seg7dig[6]" H18;
+IO_LOC "seg7dig[7]" D20;
+IO_LOC "seg7sel[0]" C19;
+IO_LOC "seg7sel[1]" B22;
+IO_LOC "seg7sel[2]" C20;
+IO_LOC "seg7sel[3]" C21;
+
+// Switches
+IO_LOC "sw[0]" AB20;
+IO_LOC "sw[1]" AB19;
+IO_LOC "sw[2]" AB18;
+IO_LOC "sw[3]" AB17;
diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v
index e1a2f19ec..6ea108384 100644
--- a/examples/gowin/demo.v
+++ b/examples/gowin/demo.v
@@ -1,11 +1,12 @@
module demo (
input clk,
- output led1, led2, led3, led4, led5, led6, led7, led8,
- output led9, led10, led11, led12, led13, led14, led15, led16
+ input [3:0] sw,
+ output [15:0] leds,
+ output [7:0] seg7dig,
+ output [3:0] seg7sel
);
localparam PRESCALE = 20;
reg [PRESCALE+3:0] counter = 0;
always @(posedge clk) counter <= counter + 1;
- assign {led1, led2, led3, led4, led5, led6, led7, led8,
- led9, led10, led11, led12, led13, led14, led15, led16} = 1 << counter[PRESCALE +: 4];
+ assign leds = 1 << counter[PRESCALE +: 4];
endmodule
diff --git a/examples/gowin/run.sh b/examples/gowin/run.sh
index 738e845e5..33a7b5c37 100644
--- a/examples/gowin/run.sh
+++ b/examples/gowin/run.sh
@@ -3,3 +3,10 @@ set -ex
yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v
$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \
-warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit
+
+# post place&route simulation (icarus verilog)
+if false; then
+ iverilog -D POST_IMPL -o testbench -s testbench testbench.v \
+ demo_out.v $(yosys-config --datdir/gowin/cells_sim.v)
+ vvp -N testbench
+fi
diff --git a/examples/gowin/testbench.v b/examples/gowin/testbench.v
new file mode 100644
index 000000000..6d206381e
--- /dev/null
+++ b/examples/gowin/testbench.v
@@ -0,0 +1,40 @@
+module testbench;
+ reg clk;
+
+ initial begin
+ #5 clk = 0;
+ forever #5 clk = ~clk;
+ end
+
+ wire [15:0] leds;
+
+ initial begin
+ // $dumpfile("testbench.vcd");
+ // $dumpvars(0, testbench);
+ $monitor("%b", leds);
+ end
+
+ demo uut (
+ .clk (clk ),
+`ifdef POST_IMPL
+ .\leds[0] (leds[0]),
+ .\leds[1] (leds[1]),
+ .\leds[2] (leds[2]),
+ .\leds[3] (leds[3]),
+ .\leds[4] (leds[4]),
+ .\leds[5] (leds[5]),
+ .\leds[6] (leds[6]),
+ .\leds[7] (leds[7]),
+ .\leds[8] (leds[8]),
+ .\leds[9] (leds[9]),
+ .\leds[10] (leds[10]),
+ .\leds[11] (leds[11]),
+ .\leds[12] (leds[12]),
+ .\leds[13] (leds[13]),
+ .\leds[14] (leds[14]),
+ .\leds[15] (leds[15])
+`else
+ .leds(leds)
+`endif
+ );
+endmodule
--
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